Section 1 8051 Microcontroller Instruction Set

1 Atmel 8051 microcontrollers Hardware10509C 8051 07/06 Section 18051 Microcontroller Instruction SetFor interrupt response time information, refer to the hardware description :1. Operations on SFR byte address 208 or bit addresses 209-215 (that is, the PSW or bits in the PSW) also affect flag that Affect Flag Settings(1)InstructionFlagInstructionFla gCOVACCOVACADDXXXCLR COADDCXXXCPL CXSUBBXXXANL C,bitXMULOXANL C,/bitXDIVOXORL C,bitXDAXORL C,/bitXRRCXMOV C,bitXRLCXCJNEXSETB C1 The Instruction Set and Addressing ModesRnRegister R7-R0 of the currently selected Register internal data location s address.

2 This could be an Internal Data RAM location (0-127) or a SFR [ , I/O port, control register, status register, etc. (128-255)].@Ri8-bit internal data RAM location (0-255) addressed indirectly through register R1or R0.#data8-bit constant included in Instruction .#data 1616-bit constant included in 1616-bit destination address. Used by LCALL and LJMP. A branch can be anywhere within the 64K byte Program Memory address 1111-bit destination address. Used by ACALL and AJMP. The branch will be within the same 2K byte page of program memory as the first byte of the following (two s complement) 8-bit offset byte.

3 Used by SJMP and all conditional jumps. Range is -128 to +127 bytes relative to first byte of the following Addressed bit in Internal Data RAM or Special Function 8051 07/06 Table 1-1. Instruction Set SummaryNote:Key: [2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle012345670 NOP JBCbit,rel[3B, 2C]JBbit, rel[3B, 2C]JNBbit, rel[3B, 2C]JCrel[2B, 2C]JNCrel[2B, 2C]JZrel[2B, 2C]JNZrel[2B, 2C]1 AJMP(P0)[2B, 2C]ACALL(P0)[2B, 2C]AJMP(P1)[2B, 2C]ACALL(P1)[2B, 2C]AJMP(P2)[2B, 2C]ACALL(P2)[2B, 2C]AJMP(P3)[2B, 2C]ACALL(P3)

4 [2B, 2C]2 LJMP addr16[3B, 2C]LCALL addr16[3B, 2C]RET[2C]RETI[2C]ORLdir, A[2B]ANLdir, A[2B]XRLdir, a[2B]ORLC, bit[2B, 2C]3 RRARRCARLARLCAORLdir, #data[3B, 2C]ANLdir, #data[3B, 2C]XRLdir, #data[3B, 2C]JMP@A + DPTR[2C]4 INCADECAADDA, #data[2B]ADDCA, #data[2B]ORLA, #data[2B]ANLA, #data[2B]XRLA, #data[2B]MOVA, #data[2B]5 INCdir[2B]DECdir[2B]ADDA, dir[2B]ADDCA, dir[2B]ORLA, dir[2B]ANLA, dir[2B]XRLA, dir[2B]MOVdir, #data[3B, 2C]6 INC@R0 DEC@R0 ADDA, @R0 ADDCA, @R0 ORLA, @R0 ANLA, @R0 XRLA, @R0 MOV@R0, @data[2B]7 INC@R1 DEC@R1 ADDA, @R1 ADDCA, @R1 ORLA, @R1 ANLA, @R1 XRLA, @R1 MOV@R1, #data[2B]8 INCR0 DECR0 ADDA, R0 ADDCA, R0 ORLA, R0 ANLA, R0 XRLA, R0 MOVR0, #data[2B]9 INCR1 DECR1 ADDA, R1 ADDCA, R1 ORLA, R1 ANLA, R1 XRLA, R1 MOVR1, #data[2B]AINCR2 DECR2 ADDA, R2 ADDCA, R2 ORLA, R2 ANLA, R2 XRLA, R2 MOVR2, #data[2B]BINCR3 DECR3 ADDA, R3 ADDCA, R3 ORLA, R3 ANLA, R3 XRLA, R3 MOVR3, #data[2B]

5 CINCR4 DECR4 ADDA, R4 ADDCA, R4 ORLA, R4 ANLA, R4 XRLA, R4 MOVR4, #data[2B]DINCR5 DECR5 ADDA, R5 ADDCA, R5 ORLA, R5 ANLA, R5 XRLA, R5 MOVR5, #data[2B]EINCR6 DECR6 ADDA, R6 ADDCA, R6 ORLA, R6 ANLA, R6 XRLA, R6 MOVR6, #data[2B]FINCR7 DECR7 ADDA, R7 ADDCA, R7 ORLA, R7 ANLA, R7 XRLA, R7 MOVR7, #data[2B]30509C 8051 07/06 Table 1-2. Instruction Set Summary (Continued)Note:Key: [2B] = 2 Byte, [3B] = 3 Byte, [2C] = 2 Cycle, [4C] = 4 Cycle, Blank = 1 byte/1 cycle89 ABCDEF0 SJMPREL[2B, 2C]MOVDPTR,#data 16[3B, 2C]ORLC, /bit[2B, 2C]ANLC, /bit[2B, 2C]PUSHdir[2B, 2C]POPdir[2B, 2C]MOVX A,@DPTR[2C]MOVX@DPTR, A[2C]1 AJMP(P4)[2B, 2C]ACALL(P4)[2B, 2C]AJMP(P5)[2B, 2C]ACALL(P5)[2B, 2C]AJMP(P6)[2B, 2C]ACALL(P6)[2B, 2C]AJMP(P7)[2B, 2C]ACALL(P7)

6 [2B, 2C]2 ANLC, bit[2B, 2C]MOVbit, C[2B, 2C]MOVC, bit[2B]CPLbit[2B]CLRbit[2B]SETBbit[2B]MO VXA, @R0[2C]MOVXwR0, A[2C]3 MOVC A,@A + PC[2C]MOVC A,@A + DPTR[2C]INCDPTR[2C]CPLCCLRCSETBCMOVXA, @RI[2C]MOVX@RI, A[2C]4 DIVAB[2B, 4C]SUBBA, #data[2B]MULAB[4C]CJNE A,#data, rel[3B, 2C]SWAPADAACLRACPLA5 MOVdir, dir[3B, 2C]SUBBA, dir[2B]CJNEA, dir, rel[3B, 2C]XCHA, dir[2B]DJNZdir, rel[3B, 2C]MOVA, dir[2B]MOVdir, A[2B]6 MOVdir, @R0[2B, 2C]SUBBA, @R0 MOV@R0, dir[2B, 2C]CJNE@R0, #data, rel[3B, 2C]XCHA, @R0 XCHDA, @R0 MOVA, @R0 MOV@R0, A7 MOVdir, @R1[2B, 2C]SUBBA, @R1 MOV@R1, dir[2B, 2C]CJNE@R1, #data, rel[3B, 2C]XCHA, @R1 XCHDA, @R1 MOVA, @R1 MOV@R1, A8 MOVdir, R0[2B, 2C]SUBBA, R0 MOVR0, dir[2B, 2C]CJNER0, #data, rel[3B, 2C]XCHA, R0 DJNZR0, rel[2B, 2C]MOVA, R0 MOVR0, A9 MOVdir, R1[2B, 2C]SUBBA, R1 MOVR1, dir[2B, 2C]CJNER1, #data, rel[3B, 2C]XCHA, R1 DJNZR1, rel[2B, 2C]MOVA, R1 MOVR1, AAMOVdir, R2[2B, 2C]SUBBA, R2 MOVR2, dir[2B, 2C]CJNER2, #data, rel[3B, 2C]XCHA, R2 DJNZR2, rel[2B, 2C]

7 MOVA, R2 MOVR2, ABMOVdir, R3[2B, 2C]SUBBA, R3 MOVR3, dir[2B, 2C]CJNER3, #data, rel[3B, 2C]XCHA, R3 DJNZR3, rel[2B, 2C]MOVA, R3 MOVR3, ACMOVdir, R4[2B, 2C]SUBBA, R4 MOVR4, dir[2B, 2C]CJNER4, #data, rel[3B, 2C]XCHA, R4 DJNZR4, rel[2B, 2C]MOVA, R4 MOVR4, ADMOVdir, R5[2B, 2C]SUBBA, R5 MOVR5, dir[2B, 2C]CJNER5, #data, rel[3B, 2C]XCHA, R5 DJNZR5, rel[2B, 2C]MOVA, R5 MOVR5, AEMOVdir, R6[2B, 2C]SUBBA, R6 MOVR6, dir[2B, 2C]CJNER6, #data, rel[3B, 2C]XCHA, R6 DJNZR6, rel[2B, 2C]MOVA, R6 MOVR6. AFMOVdir, R7[2B, 2C]SUBBA, R7 MOVR7, dir[2B, 2C]CJNER7, #data, rel[3B, 2C]XCHA, R7 DJNZR7, rel[2B, 2C]MOVA, R7 MOVR7, A8051 Microcontroller Instruction SetAtmel 8051 microcontrollers Hardware Manual1-40509C 8051 07/06 Table 1-3.

8 AT89 Instruction Set Summary(1)Note:1. All mnemonics copyrighted Intel Corp., PeriodARITHMETIC OPERATIONSADDA,RnAdd register to Accumulator112 ADDA,directAdd direct byte to Accumulator212 ADDA,@RiAdd indirect RAM to Accumulator112 ADDA,#dataAdd immediate data to Accumulator212 ADDC A,RnAdd register to Accumulator with Carry112 ADDC A,directAdd direct byte to Accumulator with Carry212 ADDC A,@RiAdd indirect RAM to Accumulator with Carry112 ADDC A,#dataAdd immediate data to Acc with Carry212 SUBBA,RnSubtract Register from Acc with borrow112 SUBBA.

9 DirectSubtract direct byte from Acc with borrow212 SUBBA,@RiSubtract indirect RAM from ACC with borrow112 SUBBA,#dataSubtract immediate data from Acc with borrow212 INCAI ncrement Accumulator112 INCRnIncrement register112 INCdirectIncrement direct byte212 INC@RiIncrement direct RAM112 DECAD ecrement Accumulator112 DECRnDecrement Register112 DECdirectDecrement direct byte212 DEC@RiDecrement indirect RAM112 INCDPTRI ncrement Data Pointer124 MULABM ultiply A & B148 DIVABD ivide A by B148 DAAD ecimal Adjust Accumulator112 MnemonicDescriptionByteOscillator PeriodLOGICAL OPERATIONSANLA.

10 RnAND Register to Accumulator112 ANLA,directAND direct byte to Accumulator212 ANLA,@RiAND indirect RAM to Accumulator112 ANLA,#dataAND immediate data to Accumulator212 ANLdirect,AAND Accumulator to direct byte212 ANLdirect,#dataAND immediate data to direct byte 324 ORLA,RnOR register to Accumulator112 ORLA,directOR direct byte to Accumulator212 ORLA,@RiOR indirect RAM to Accumulator 112 ORLA,#dataOR immediate data to Accumulator212 ORLdirect,AOR Accumulator to direct byte212 ORLdirect,#dataOR immediate data to direct byte324 XRLA,RnExclusive-OR register to Accumulator112 XRLA,directExclusive-OR direct byte to Accumulator212 XRLA,@RiExclusive-OR indirect RAM to Accumulator112 XRLA,#dataExclusive-OR immediate data to Accumulator212 XRLdirect,AExclusive-OR Accumulator to direct byte212 XRLdirect.