SLVSB82A - Texas Instruments

1 To 18V Input, Synchronous Step-Down Converter1 Features D-CAP2 mode enables fast transient response Low output ripple and allows ceramic outputcapacitor Wide VIN input voltage range: V to 18 V Output voltage range: V to V Highly efficient integrated FETs optimizedfor lower duty cycle applications 63 m (high side) and 33 m (low side) High efficiency, less than 10 A at shutdown High initial bandgap reference accuracy Adjustable soft start Pre-biased soft start 650-kHz switching frequency (fSW) Cycle-by-cycle overcurrent limit Power good output2 Applications Wide range of applications for low voltage system Digital TV power supply High definition Blu-ray Disc players Networking home terminal Digital set top box (STB)

2 3 DescriptionThe TPS54525 is an adaptive on-time D-CAP2 mode synchronous buck converter. The TPS54525enables system designers to complete the suiteof various end equipment s power bus regulatorswith a cost effective, low component count, lowstandby current solution. The main control loop forthe TPS54525 uses the D-CAP2 mode controlwhich provides a very fast transient response with noexternal compensation components. The TPS54525also has a proprietary circuit that enables the deviceto adopt to both low equivalent series resistance(ESR) output capacitors, such as POSCAP or SP-CAP, and ultra-low ESR ceramic capacitors.

3 Thedevice operates from to 18-V VIN input. Theoutput voltage can be programmed between Vand V. The device also features an adjustable softstart time and a power good function. The TPS54525is available in the 14-pin HTSSOP package, anddesigned to operate from 40 C to 85 InformationPART NUMBERPACKAGEBODY mm mmU1 TPS54525 Slew Rate ( sec)V (50 mV/div ac coupled)OI(2A/div)OUTTime Scale (100 sec/div) MAY 2012 REVISED APRIL 2021 Copyright 2021 Texas Instruments IncorporatedSubmit Document Feedback1 Product Folder Links: TPS54525 TPS54525 SLVSB82B MAY 2012 REVISED APRIL 2021An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers.

4 PRODUCTION of Contents1 Revision Pin Configuration and Absolute Maximum ESD Recommended Operating Thermal Electrical Typical Detailed Functional Block Feature Device Functional Application and Application Typical Power Supply Layout Layout Device and Documentation Device Receiving Notification of Documentation Support Electrostatic Discharge Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current from Revision A (July 2013) to Revision B (April 2021)Page Added the following sections: ESD Ratings, Feature Description, Device Functional Modes, Force CCMMode, Application and Implementation, Application Information, Design Requirements, Detailed DesignProcedure, Application Curves, Power Supply Recommendations, Layout, Layout Example, Device andDocumentation Support, and Mechanical, Packaging, and Orderable Information.

5 1 Updated the numbering format for tables, figures, and cross-references throughout the document..1 Updated Equation 2 ..14 Changes from Revision May 2012 * () to Revision A (July 2013)Page Deleted VFBTH - TA = 0 C to 85 C, VO = V, continuous mode from the Electrical Characteristics..5 Changed VFBTH - TA = 40 C to 85 C, VO = V, continuous mode From: MIN = 751 MAX = 779 mV To:MIN = 754 MAX = 776 mV in the Electrical Changed the Over/Under Voltage Protection section. From: "as the high-side MOSFET driver turns off andthe low-side MOSFET turns on" To: "as both the high-side and low-side MOSFET drivers turn off".

6 12 TPS54525 SLVSB82B MAY 2012 REVISED APRIL Document FeedbackCopyright 2021 Texas Instruments IncorporatedProduct Folder Links: TPS545255 Pin Configuration and FunctionsPOWER PADTPS54525 PWPHTSSOP14SW1 VBSTSSVOVFBGNDPGND1147562341 VIN2 ENPGVREG513121198 PGND210SW2 VIN1 PWP PACKAGE(TOP VIEW)Table 5-1. Pin to output of converter. This pin is used for output discharge feedback input. Connect to output voltage with feedback resistor V power supply output. A capacitor (typical 1 F) should be connected to GND. VREG5 is not activewhen EN is control. An external capacitor should be connected to ground pinPG6 Open drain power good outputEN7 Enable control input.

7 EN is active high and must be pulled up to enable the , PGND28, 9 Ground returns for low-side MOSFET. Also serve as inputs of current comparators. Connect PGND andGND strongly together near the , SW210, 11 Switch node connection between high-side NFET and low-side NFET. Also serve as inputs to input for high-side NFET gate driver (boost terminal). Connect capacitor from this pin torespective SW1, SW2 terminals. An internal PN diode is connected between VREG5 to VBST , VIN213, 14 Power input and connected to high side NFET drain. Supply input for 5-V internal linear regulator for thecontrol Back sideThermal pad of the package.

8 Must be soldered to achieve appropriate dissipation. Should be connectedto MAY 2012 REVISED APRIL 2021 Copyright 2021 Texas Instruments IncorporatedSubmit Document Feedback3 Product Folder Links: TPS545256 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)MINMAXUNITI nput voltage rangeVIN1, VIN2 EN (10 ns transient) (vs SW1, SW2) , VO, SS, PG , SW2 220 VSW1, SW2 (10 ns transient) 322 VOutput voltage rangeVREG5 , PGND2 from GND to PowerPAD , Vdiff junction temperature, TJ 40150 C(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device.

9 These are stress ratingsonly, and functional operation of the device at these or any other conditions beyond those indicated under recommended operatingconditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device ESD RatingsVALUEUNITMINMAXS torage temperature, Tstg-55150 CV (ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)-20002000 VCharged-device model (CDM), per JEDEC specification JESD22-C101(2)-500500(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

10 (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control MAY 2012 REVISED APRIL Document FeedbackCopyright 2021 Texas Instruments IncorporatedProduct Folder Links: Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)MINMAXUNITVINS upply input voltage voltage rangeVBST (10 ns transient) (vs SW1, SW2) , PG , VFB , SW2 , SW2 (10 ns transient) 321 PGND1, PGND2 voltage rangeVREG5 Current rangeIVREG505mATAO perating free-air temperature 4085 CTJO perating junction temperature 40150 Thermal InformationTHERMAL METRIC(1)TPS54525 UNITSPWP14 PINS JAJunction-to-ambient thermal C/W JCtopJunction-to-case (top)