SLVSBR5C –DECEMBER 2012–REVISED JUNE 2015 …

1 ESDESDESDL ogic &ControlTPS27082L(4)(6)(5)(2, 3)RS= C1 VOUTVINR1/C1ON/OFFR1 GND(1)ESDQ1Q2 ProductFolderSample &BuyTechnicalDocumentsTools &SoftwareSupport &CommunityReferenceDesignTPS27082 LSLVSBR5C DECEMBER2012 to 8-V, 3-A PFET Load SwitchWith ConfigurableSlew Rate, FastTransientIsolationand HystereticControl1 Features2 Applications1 Low ON-Resistance,HighCurrentPFET High-SideLoadSwitches Inrush-currentControls RON= 32 m (Typical)at VGS= V PowerSequencingand Controls RON= 44 m (Typical)at VGS= V Stand-byPowerIsolation RON= 85 m (Typical)at VGS= V PortablePowerSwitches RON= 97 m (Typical)at VGS= V RON= 155 m (Typical)

2 At VGS= V3 Description ConfigurableTurn-ONand Turn-OFFSlewRateTheTPS27082 LIC is a high-sideloadswitchthat 10- s DefaultMinimumOutputRiseTimeatintegrates a PowerPFETand a controlcircuitin aVIN=5 Vtiny low ConfigurableTurnonand TurnoffSlewRateON-statequiescentcurrenta nd offersverylow OFF-stateleakagethusoptimizingsystempowe r Supportsa WideRangeof VIN V Up to 8 Vefficiency. ExcellentOFFI solationEvenUnderFastInputTPS27082 LON/OFFlogicinterfacefeaturesTransientsh ysteresis,thusprovidinga robustlogicinterface to 8V FullyProtectedAgainstESD(All Pins)interfacingto low voltageGPIO sdownto 1 V.

3 TheTPS27082 LlevelshiftsON/OFFlogicsignalto VIN HBM2000V, CDM500 Vlevelswithoutrequiringan externallevelshifter. VeryLow ON-stateQuiescentCurrent( A)TPS27082 Lfeaturesa novelOFFisolationcircuitthatpreventsPMOS fromturningON in applicationsthat VeryLow OFF-stateLeakageCurrent(Typicalmayhavefa st transients,at the VIN pin whenthe100 nA)load switchis in the OFF-state. Availablein mm mm x (DDC)PackageDeviceInformation(1)PARTNUMB ERPACKAGEBODYSIZE(NOM)TPS27082 DDCSOT(6) (1) For all availablepackages,see the orderableaddendumatthe end of the IMPORTANTNOTICEat the end of this datasheetaddressesavailability,warranty, changes,use in safety-criticalapplications,intellectual propertymattersand DECEMBER2012 Applicationand Pin Configurationand Deviceand Mechanical,Packaging,and RevisionHistoryNOTE.

4 Pagenumbersfor previousrevisionsmay differfrompagenumbersin the (September2013)to RevisionCPage AddedPin Configurationand Functionssection,StorageConditionstable, ESDR atingstable,FeatureDescriptionsection,De viceFunctionalModes,Applicationand Implementationsection,PowerSupplyRecomme ndationssection,Layoutsection,Deviceand DocumentationSupportsection,andMechanica l,Packaging,and (April2013)to RevisionBPage FixedUNIT typo for (December2012)to RevisionAPage Updatedwordingin the 2012 2015,TexasInstrumentsIncorporatedProduct FolderLinks.

5 TPS27082 LVOUT123 GNDVOUTVIN654R1/C1 DECEMBER2012 REVISEDJUNE20155 Pin Configurationand FunctionsDDCP ackage6-PinSOTTop ViewPin the systemGND2 DrainTerminalof PowerPFET(Q1) If required,connecta slewcontrolcapacitorbetweenpins VOUTVOUTOand R1/C3 VIN4 ISourceTerminalof PowerPFET(Q1) connecta pull-upresistorbetweenthe pins VIN and R1/C1 Activehigh enable whendrivenwith a high impedancedriver,connectan externalpull downresistortoON/OFF5 IGNDR1/C16 IGateTerminalof PowerPFET(Q1)Copyright 2012 2015,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback3 ProductFolderLinks.

6 TPS27082 LTPS27082 LSLVSBR5C DECEMBER2012 TJ= 40 C to 125 C (unlessotherwisenoted)(1)(2)(3)MINMAXUNI TVINmax,VIN,VOUTpin maximumvoltagewith respectto GNDpin continuousdraincurrentof Q13IQ1-ONAMax pulseddraincurrentof Q1(4) powerdissipationat TA= 25 C, TJ= 150 C(4)6 Pin-TSOT,R JA=105 C/W1190mWTAO peratingfree-airambienttemperature-40125 (5) CTJ-maxOperatingvirtualjunctiontemperatu re150 CTstgStoragetemperature 65150 C(1)StressesbeyondthoselistedunderAbsolu teMaximumRatingsmay causepermanentdamageto the stressratingsonly,whichdo not implyfunctionaloperationof the deviceat theseor any otherconditionsbeyondthoseindicatedunder RecommendedOperatingConditions.

7 Exposureto absolute-maximum-ratedconditionsfor extendedperiodsmay affectdevicereliability.(2)Operatingat the absoluteTJ-maxof 150 C can affectreliability for higherreliabilityit is recommendedto ensureTJ< 125 C(3)Referto TI s designsupportweb pageat improvingdevicethermalperformance.(4)Pul seWidth< 300 s, DutyCycle< 2%(5)TJ-maxlimitsand SOAcharts,Figure8 (HBM),per ANSI/ESDA/JEDECJS-001,all pins(1) 2000V(ESD)ElectrostaticdischargeVCharged devicemodel(CDM),per JEDEC specificationJESD22-C101, 500all pins(2)(1)JEDEC documentJEP155statesthat 500-VHBM allowssafe manufacturingwith a standardESDcontrolprocess.

8 (2)JEDEC documentJEP157statesthat 250-VCDM allowssafe manufacturingwith a (unlessotherwisenoted)MINMAXUNITVINI nputVoltageRange18 VTAO peratingfree-airambienttemperaturerange- 4085 CTJJ unctionTemperature-40105 (1)DDC(SOT)UNIT6 PINSR JAJunction-to-ambientthermalresistance10 5 C/WR JC(top)Junction-to-case(top)thermalresis tance43 C/WR C/W C/W C/WR JC(bot)Junction-to-case(bottom)thermalre sistance C/W(1)For moreinformationabouttraditionaland new thermalmetrics,see theSemiconductorand IC PackageThermalMetricsapplicationreport, 2012 2015, DECEMBER2012 temperaturerangespansTJ= 40 C to 125 C (unlessotherwisenoted)FULLTEMPTA=TJ= 25 CRANGE(1)PARAMETERTESTCONDITIONSUNITMINT YPMAXMINMAXOFFCHARACTERISTICSVON/OFF= 0 V, VGS(Q1)= 0 V,BVINVIN breakdownvoltage 8 8 VID(Q1)= 250 AVIN = 8 V, ON/OFF= 0 V, = IFINVIN pin total forwardleakagecurrent(2) AVIN = 5 V, ON/OFF= 0 V, = ON CHARACTERISTICS(3)VIN = V, R1 = 125 k (1)

9 , = VT+PositivegoingON/OFFthresholdVvoltage( 4)(VIH)VIN = V, R1 = 1 M , = VIN = V, ID(Q1)< 175 A,400R1 =125k (1)VT NegativegoingON/OFFthresholdmVvoltage(4) (VIL)VIN = V, ID(Q1)< 175 A,270R1 = 1 M VIN = V, R1 = 125 k (1)600 VTON/OFFinputlogichysteresis(4)mV(VT+ VT )VIN = V, R1 = 1 M 730 VGSQ1= ,ID = A325264 VGS1Q1= ,ID =2 .5 A446684 VGS1Q1= ,ID = A507692RQ1(ON)Q1 ChannelON resistance(5)m VGSQ1= ,ID = A82113147 VGSQ1 = ,ID = A97150173 VGSQ1= ,ID = to GNDpin resistancewhenRGNDONVON/OFF= Q2 is ONQ1 DRAIN-SOURCEDIODEPARAMETERS(1)(3)(6)IFSD S ource-draindiodepeakforwardcurrentVFSD(Q 1)= ,VON/OFF= 0 V1 AVFSDS ource-draindiodeforwardvoltageIFSD(Q1)= ,VON/OFF= 0 (1)Specifiedby designonly(2)Referto IFVIN plotsfor moreinformation(3)Pulsewidth< 300 s, Dutycycle< 2%(4)Referto chartsfor moreinformationon VT+/VT thresholds(5)

10 Referto SOAchartsfor operatingcurrentinformation(6)Not ratedfor (1)(2)(3).DERATINGFACTORBOARDPACKAGER JCR JA(4)TA< 25 CTA= 70 CTA= 85 CTA= 105 CABOVETA= 25 CHigh-K6-PinTSOT43 C/W105 C/W1190mW760 mW619 mW428 C(JEDEC51-7)(DDC)(1)Maximumdissipationva luesfor retaininga maximumallowabledevicejunctiontemperatur eof 150 C(2)Referto TI s designsupportweb pageat improvingdevicethermalperformance(3)Pack agethermaldatabasedon a ,4-layerboardwith 2-ozCopperon outerlayers(4)Operatingat the absoluteTJ-maxof 150 C can affectreliability;TJ 125 C is recommendedCopyright 2012 2015,TexasInstrumentsIncorporatedSubmitD ocumentationFeedback5 ProductFolderLinks:TPS27082 LTPS27082 LSLVSBR5C DECEMBER2012 Vdropvs IL; VGS_Q1= VFigure2.