SMP18 Octal Sample-and-Hold with Multiplexed …

1 REV. CInformation furnished by analog devices is believed to be accurate andreliable. However, no responsibility is assumed by analog devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of analog Sample-and-Holdwith Multiplexed InputSMP18 FUNCTIONAL BLOCK DIAGRAMSWSWSWSWSWSWSWSW1 OF 8 DECODER69101131316814151271245 DGNDVDDCH0 OUTCH1 OUTCH2 OUTCH3 OUTCH4 OUTCH5 OUTCH6 OUTCH7 OUTVSSHOLD CAPS(INTERNAL) SMP18 INPUT(LSB)AB(MSB)CINHFEATURESHigh Speed Version of SMP08 Internal hold CapacitorsLow Droop RateTTL/CMOS Compatible Logic InputsSingle or Dual Supply OperationBreak-Before-Make Channel AddressingCompatible with CD4051 PinoutLow CostAPPLICATIONSM ultiple Path Timing Deskew for ProgrammersMass Flow/Process Control SystemsMultichannel Data Acquisition SystemsRobotics and Control SystemsMedical and Analytical InstrumentationEvent AnalysisStage Lighting ControlGENERAL DESCRIPTIONThe SMP18 is a monolithic Octal Sample-and-Hold ; it has eightinternal buffer amplifiers, input multiplexer, and internal holdcapacitors.

2 It is manufactured in an advanced oxide isolatedCMOS technology to obtain high accuracy, low droop rate, andfast acquisition time. The SMP18 has a typical linearity error ofonly and can accurately acquire a 10-bit input signal to 1/2 LSB in less than microseconds. The SMP18 s outputswing includes the negative supply in both single and dual sup-ply SMP18 was specifically designed for systems that use acalibration cycle to adjust a multiple of system parameters. Thelow cost and high level of integration make the SMP18 ideal forcalibration requirements that have previously required an ASIC,or high cost multiple D/A SMP18 is also ideally suited for a wide variety of Sample-and-Hold applications including amplifier offset or VCA gain ad-justments. One or more SMP18s can be used with single ormultiple DACs to provide multiple set points within a SMP18 offers significant cost and size reduction overdiscrete designs.

3 It is available in a 16-pin plastic DIP, anarrow body SO-16 surface-mount SOIC package or the thinTSSOP-16 package. The SMP18 is a higher speed directreplacement for the Technology Way, Box 9106, Norwood, MA 02062-9106, : 617/329-4700 World Wide Web Site: : 617/326-8703 analog devices , Inc., 1996 ELECTRICAL CHARACTERISTICSP arameterSymbolConditionsMinTypMaxUnitsLi nearity Error 3 V VIN +3 Offset VoltageVOSTA = +25 C, VIN = 0 40 C TA +85 C, VIN = 0 StepVHSVIN = 0 V, TA = +25 C to +85 C46mVVIN = 0 V, TA = 40 C8mVDroop Rate VCH/ tTA = +25 C, VIN = 0 V240mV/sOutput Source CurrentISOURCEVIN = 0 Sink CurrentISINKVIN = 0 Voltage RangeRL = 20 k + CHARACTERISTICSL ogic Input High Input Low Input CurrentIINVIN = ADYNAMIC PERFORMANCE2 Acquisition Time3tAQTA = +25 C.

4 3 V to +3 V to sHold Mode Settling TimetHTo 1 mV of Final Value1 sChannel Select TimetCH90nsChannel Deselect TimetDCS45nsInhibit Recovery TimetIR90nsSlew RateSR6V/ sCapacitive Load Stability<30% Overshoot500pFAnalog Crosstalk 3 V to +3 V Step 72dBSUPPLY CHARACTERISTICSP ower Supply Rejection RatioPSRRVSS = 5 V to 6 V6075dBSupply CurrentIDDTA = +25 40 C TA +85 CHARACTERISTICSP arameterSymbolConditionsMinTypMaxLimitsL inearity Error60 mV VIN 10 Offset VoltageVOSTA = +25 C, VIN = 6 40 C TA +85 C, VIN = 6 StepVHSVIN = 6 V, TA = +25 C to +85 C46mVVIN = 6 V, TA = 40 C8mVDroop Rate VCH/ tTA = +25 C, VIN = 6 V240mV/sOutput Source CurrentISOURCEVIN = 6 Sink CurrentISINKVIN = 6 Voltage RangeRL = 20 k = 10 k CHARACTERISTICSL ogic Input High Input Low Input CurrentIINVIN = ADYNAMIC PERFORMANCE2 Acquisition Time3tAQTA = +25 C, 0 to 10 V to sHold Mode Settling TimetHTo 1 mV of Final Value1 sChannel Select TimetCH90nsChannel Deselect TimetDCS45nsInhibit Recovery TimetIR90nsSlew Rate4SR7V/ sCapacitive Load Stability<30% Overshoot500pFAnalog Crosstalk0 V to 10 V Step 72dBSUPPLY CHARACTERISTICSP ower Supply Rejection V VDD V6075dBSupply CurrentIDDTA = +25 40 C TA +85 are capable of sinking and sourcing over 10 mA but offset is guaranteed at specified load input control signals are specified with tr = tf = 5 ns (10% to 90% of +5 V)

5 And timed from a voltage level of parameter is guaranteed without rate is measured in the sample mode with a 0 to 10 V step from 20% to 80%.Specifications subject to change without C 2 SMP18 SPECIFICATIONS(@ VDD = +5 V, VSS = 5 V, DGND = 0 V, RL = No Load, TA = 408C to +858C for SMP18F,unless otherwise noted)(@ VDD = +12 V, VSS = 0 V, DGND = 0 V, RL = No Load, TA = 408C to +858C for SMP18F,unless otherwise noted) SMP18 REV. C 3 PIN CONNECTIONS14131211161510981234765 TOP VIEW(Not to Scale)SMP18CH4 OUTCH0 OUTCH1 OUTCH2 OUTVDDCH6 OUTINPUTCH7 OUTB CONTROLA CONTROLCH3 OUTCH5 OUTINHVSSDGNDC CONTROLORDERING GUIDET emperaturePackagePackageModelRangeDescri ptionOptionSMP18FP 40 C to +85 CPlastic DIPN-16 SMP18 FRU 40 C to +85 CTSSOP-16RU-16 SMP18FS 40 C to +85 CSO-16R-16 AABSOLUTE MAXIMUM RATINGSVDD to DGND.

6 V, 17 VVDD to VSS .. V, 17 VVLOGIC to DGND .. V, VDDVIN to DGND .. VSS, VDDVOUT to DGND .. VSS, VDDA nalog Output Current .. 20 mA(Not short-circuit protected)Operating Temperature RangeFP, FS .. 40 C to +85 CJunction Temperature .. +150 CStorage Temperature .. 65 C to +150 CLead Temperature (Soldering, 60 sec) .. +300 CPackage TypeuJA*uJCUnits16-Pin Plastic DIP (P)7633 C/W16-Pin SOIC (S)9227 C/W16-Lead TSSOP (RU)18035 C/WNOTES* JA is specified for worst case mounting conditions, , JA is specified for devicein socket for plastic DIP packages; JA is specified for device soldered to printedcircuit board for SOIC and TSSOP !ESD SENSITIVE DEVICECAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without the SMP18 features proprietary ESD protection circuitry, permanent damage mayoccur on devices subjected to high energy electrostatic discharges.

7 Therefore, proper ESDprecautions are recommended to avoid performance degradation or loss of C 4 TEMPERATURE CDROOP RATE 40 201000 = +12 VVSS = 0 VVIN = +6 VRL = 10k Droop Rate vs. TemperatureINPUT VOLTAGE VoltsHOLD STEP mV0 3 6011023456789 1 2 4 5 VDD = +12 VVSS = 0 VTA = +25 CNO LOADHold Step vs. Input VoltageINPUT VOLTAGE VoltsOFFSET VOLTAGE mV4 1001102345678920 2 4 6 8 VDD = +12 VVSS = 0 VTA = +25 CRL = RL = 20k RL = 10k Offset Voltage vs. Input Voltage Typical Performance CharacteristicsINPUT VOLTAGE VoltsDROOP RATE mV/s53 5011023 4 5 67 8 91 1 3 VDD = +12 VVSS = 0 VTA = +25 CNO LOADD roop Rate vs. Input VoltageTEMPERATURE CHOLD STEP mV1 7 55 35125 155256585 105450 3 4 5 6 1 2 VDD = +12 VVSS = 0 VVIN = 6 VNO LOADHold Step vs.

8 TemperatureINPUT VOLTAGE VoltsOFFSET VOLTAGE mV205 200110234567891510 5 150 10 VDD = +12 VVSS = 0 VTA = +85 CRL = RL = 20k RL = 10k Offset Voltage vs. Input VoltageINPUT VOLTAGE VoltsDROOP RATE mV/s1307010011023456789110905030 VDD = +12 VVSS = 0 VTA = +85 CNO LOADD roop Rate vs. Input VoltageVDD VoltsSLEW RATE V/ s300101118121314151617252015105 VDD = +12 VVSS = 0 VTA = +25 CNO LOAD+SR SRSlew Rate vs. VDDINPUT VOLTAGE VoltsOFFSET VOLTAGE mV4 1001102345678920 2 4 6 8 VDD = +12 VVSS = 0V TA = 40 CRL = RL = 20k RL = 10k Offset Voltage vs. Input VoltageSMP18 REV. C 5 TEMPERATURE COFFSET VOLTAGE mV0 8 55 35125 155256585 10545 1 4 5 6 7 2 3 VDD = +12 VVSS = 0 VVIN = +5 VRL = 10k Offset Voltage vs. TemperatureVDD VoltsSUPPLY CURRENT mA14246188 101214161210864 VSS = 0 VNO LOAD+85 C+25 C 40 CSupply Current vs.

9 VDDT ypical Performance Characteristics FREQUENCY Hz90800101001M1k10k100k70602050403010 REJECTION RATIO dBVDD = +12 VVSS = 0 VVIN = +6 VTA = +25 CNO LOAD+PSRR PSRRS ample Mode Power Supply RejectionFREQUENCY HzGAIN dB21 51001k10M10k100k1M0 1 2 3 49045 2250 45 90 135 180 PHASE SHIFT DegreesVDD = +6 VVSS = 6 VTA = +25 CNO LOADGAINPHASEGain, Phase Shift vs. FrequencyFREQUENCY HzPEAK-TO-PEAK OUTPUT Volts1512010k100k10M1M963 VDD = +6 VVSS = 6 VTA = +25 CNO LOADM aximum Output Voltage HzOUTPUT IMPEDANCE 35300101001M1k10k100k252015105 VDD = +12 VVSS = 0 VTA = +25 CNO LOADO utput Impedance vs. FrequencyFREQUENCY HzREJECTION RATIO dB6050 10101001M1k10k100k403020100 VDD = +12 VVSS = 0 VTA = +25 CNO LOAD+PSRRHOLD CAPACITORS REFERENCED TO VSS PSRRHold Mode Power Supply RejectionSMP18 REV.

10 C 6 14131211161510981234765 SMP18R32k R41k R110 D1C110 FC21 F+VCC+15VR210k R210k R210k R210k R210k R210k R210k R210k Burn-in CircuitAPPLICATIONS INFORMATIONThe SMP18 , a Multiplexed Octal S/H, minimizes board spacein systems requiring cycled calibration or an array of controlvoltages. When used in conjunction with a low cost 16-bit D/A,the SMP18 can easily be integrated into microprocessor basedsystems. Since the SMP18 features break-before-make switchingand an internal decoder, no external logic is required. TheSMP18 has an internally regulated TTL supply so thatTTL/CMOS compatibility is maintained over the full supplyrange. See Figure 1 for channel decode address SUPPLIESThe SMP18 is capable of operating with either single or dualsupplies over a voltage range of 7 to 15 volts.