SN74LV8154 Dual 16-Bit Binary Counters With 3 …

1 CCKBCCKBENRCLKCCKACCLRRRRRRRRRRRRRRRRRRR RRRRRRRRRRRRRR16-Bit Counter B16-Bit Counter AGALGAUGBLGBU4 to 1 Dec4 to 1 Dec4 to 1 Dec4 to 1 Dec4 to 1 Dec4 to 1 Dec4 to 1 Dec4 to 1 DecY0Y1Y2Y3Y4Y5Y6Y7 RCOAP roductFolderOrderNowTechnicalDocumentsTo ols &SoftwareSupport &CommunityAn IMPORTANTNOTICEat the end of this datasheetaddressesavailability,warranty, changes,use in safety-criticalapplications,intellectual propertymattersand AUGUST2004 REVISEDMAY2020SN74LV8154 Dual 16-BitBinaryCountersWith 3-StateOutputRegistersCheckfor Samples:SN74LV815411 Features1 Can Be Usedas Two 16-BitCountersor a Single32-BitCounter 8-bitcounterreadbus 2-V to Maximumtpdof 25 ns at 5 V (RCLKto Y) TypicalVOLP(OutputGroundBounce)< V at VCC= 5 V, TA= 25 C TypicalVOHV(OutputVOHU ndershoot)> V at VCC= 5 V, TA= 25 C IoffSupportsPartial-Power-DownModeOperat ion Latch-UpPerformanceExceeds250 mAPer JESD17 ESDP rotectionExceedsJESD22 2000-VHumanBodyModel(A114-A) 200-VMachineModel(A115-A) 1000-VCharged-DeviceModel(C101)

2 2 Applications Up Counters DualUp Counters3 DescriptionTheSN74LV8154deviceis a dual16-bitbinarycounterwith 3-stateoutputregisters,designedfor 2-Vto clockedstorageregisterto sampleand savethe be mappedon the outputbus 8-bitsat neededto accessthecontentsof two counterscanbe chainedby connectingCLKBENto fullyspecifiedfor partial-power-downapplicationsusingIoff. TheIoffcircuitrydisablestheoutputs,preve ntingdamagingcurrentbackflowthroughthe devicewhenit is (1)PARTNUMBERPACKAGEBODYSIZE(NOM)SN74LV8 154 NPDIP(20) x (20) x (1) For all availablepackages,see the orderableaddendumatthe end of the AUGUST2004 : SN74LV8154 SubmitDocumentationFeedbackCopyright 2004 2020,TexasInstrumentsIncorporatedTableof Contents1 Pin Configurationand VCC= V 5 V Applicationand Deviceand Mechanical,Packaging,and RevisionHistoryNOTE.

3 Pagenumbersfor previousrevisionsmay differfrompagenumbersin the (October2015)to RevisionBPage Changedbodysize in Changedbodysize in Correctedtypo 'acitve-low' to active-lowin the Pin (August2004)to RevisionAPage AddedPin Configurationand Functionssection,StorageConditionstable, ESDR atingstable,FeatureDescriptionsection,De viceFunctionalModes,Applicationand Implementationsection,PowerSupplyRecomme ndationssection,Layoutsection,Deviceand DocumentationSupportsection,andMechanica l,Packaging,and AUGUST2004 REVISEDMAY2020 ProductFolderLinks: SN74LV8154 SubmitDocumentationFeedbackCopyright 2004 2020,TexasInstrumentsIncorporated5 Pin Configurationand FunctionsN or PW Package20-PinPDIPor TSSOPTop ViewTable1.

4 Pin ,asyncrounousactive-lowclearfor bothcountersCLKA1 IClockA, risingedgecountclockCLKB2 IClockB, risingedgecountclockCLKBEN9 IClockB enable,active-lowallowsclockingfor counterB; connectto RCOAfor lowerbyte,active-lowputs lowerbyte of storedcounterA on the Y upperbyte,active-lowputs upperbyte of storedcounterA on the Y lowerbyte,active-lowputs lowerbyte of storedcounterB on the Y upperbyte,active-lowputs upperbyte of storedcounterB on the Y GroundRCLK7 IRegisterClock,risingedgestorescountersi nto an , activelow whencounterA is full countand readyto overflowon PowersupplypinY019 ODataoutputbit 0 (LSB)Y118 ODataoutputbit 1Y217 ODataoutputbit 2Y316 ODataoutputbit 3Y415 ODataoutputbit 4Y514 ODataoutputbit 5Y613 ODataoutputbit 6Y712 ODataoutputbit 7 (MSB)4SN74LV8154 SCLS589B AUGUST2004.

5 SN74LV8154 SubmitDocumentationFeedbackCopyright 2004 2020,TexasInstrumentsIncorporated(1)Stre ssesbeyondthoselistedunderAbsoluteMaximu mRatingsmay causepermanentdamageto the stressratingsonly,whichdo not implyfunctionaloperationof the deviceat theseor any otherconditionsbeyondthoseindicatedunder RecommendedOperatingConditions. Exposureto absolute-maximum-ratedconditionsfor extendedperiodsmay affectdevicereliability.(2)The inputand outputvoltageratingsmay be exceededif the inputand outputcurrentratingsare observed.(3)This valueis limitedto V (unlessotherwisenoted)(1)MINMAXUNITVCCS upplyvoltage (2) any outputin the high-impedanceor power-offstate(2) (2)(3) + < 0 20mAIOKO utputclampcurrentVO< 0 50mAIOC ontinuousoutputcurrentVO= 0 to VCC 35mAContinuouscurrentthroughVCCor GND 70mATJJ unctionTemperature150 CTstgStoragetemperature 65150 C(1)JEDEC documentJEP155statesthat 500-VHBM allowssafe manufacturingwith a standardESDcontrolprocess.

6 (2)JEDEC documentJEP157statesthat 250-VCDM allowssafe manufacturingwith a (ESD)ElectrostaticdischargeHumanbodymode l(HBM),per ANSI/ESDA/JEDECJS-001,all pins(1) 2000 VChargeddevicemodel(CDM),per JEDEC specificationJESD22-C101,all pins(2) 1000(1)All unusedinputsof the devicemustbe held at VCCor GNDto the TI applicationreport,Implicationsof Slowor FloatingCMOSI nputs, (1) V to VVCC V to VVCC V to VVCC V to VVCC low V 50 A3 V to V V to V 12 IOLLow-leveloutputcurrent2 V50 A3 V to V to V12 t/ vInputtransitionrise and fall rate3 V to V100 V to V20 TAOperatingfree-airtemperature 4085 AUGUST2004 REVISEDMAY2020 ProductFolderLinks: SN74LV8154 SubmitDocumentationFeedbackCopyright 2004 2020,TexasInstrumentsIncorporated(1)For moreinformationabouttraditionaland new thermalmetrics,see theSemiconductorand IC PackageThermalMetricsapplicationreport(S PRA953).

7 (1) SN74LV8154 NSN74LV8154 PWUNITN (PDIP)PW (TSSOP)20 PINS20 PINSR C/WR JC(top)Junction-to-case(top) C/WR C/W C/W (unlessotherwisenoted)PARAMETERTESTCONDI TIONSVCCMINTYPMAXUNITVOHO utputhigh voltageIOH= 50 A2 6 mA3 12 voltageIOL= 50 A2 6 mA3 12 V or GND0 to V 1 AIOZO utputoff currentVO= VCCor V 5 AICCS upplycurrentVI= VCCor GND,IO= V20 AIoffOff currentVIor VO= 0 to V05 ACII nputcapacitanceVI= VCCor GND5 V3pFCoOutputcapacitanceVO= VCCor GND5 V5pFCpdPowerdissipationcapacitanceCL= No load,CCLK= 10 MHzRCLK= 1 MHz5 V56pF(1)tzcondition:CL= 50 pF, RL= 1 k ,VCC= 5 V V (unlessotherwisenoted)(seeFigure3)MINUNI TtwPulsedurationCLKA,CLKB,RCLK high or low10nsCCLRlow20tsuSet-uptimeCLKBENlow beforeCLKB 10nsCCLR high (inactive)beforeCLKA or CLKB 10 CLKA or CLKB beforeRCLK 10 RCLK beforeGALor GAUor GBLor GBUlow10 GALor GAUor GBLor GBUhigh (inactive)beforeRCLK 10thHoldtimeCLKBENlow afterCLKB 0nsCLKAor CLKB afterRCLK0tz(1)Z-periodGAL,GAU,GBL,GBUal l high beforeone of themswitcheslow200ns6SN74LV8154 SCLS589B AUGUST2004.

8 SN74LV8154 SubmitDocumentationFeedbackCopyright 2004 2020, VCC= V Voverrecommendedoperatingfree-airtempera turerange,VCC= V V (unlessotherwisenoted)(seeFigure3)PARAME TERFROM(INPUT)TO(OUTPUT)LOADCAPACITANCEM INTYPMAXUNITfMAXCL= 15 pF40 MHzCL= 50 pF25tpdRCLKYCL= 15 pF12238nsCLKARCOA12644tPLHCCLRRCOA11832n stenGAL,GAU,GBL,GBUY12746nstdisGAL,GAU,G BL,GBUY11221nstpdRCLKYCL= 50 pF12542nsCLKARCOA12846tPLHCCLRRCOA12035n stenGAL,GAU,GBL,GBUY13050nstdisGAL,GAU,G BL, 5 V Voverrecommendedoperatingfree-airtempera turerange,VCC= 5 V V (unlessotherwisenoted)(seeFigure3)PARAME TERFROM(INPUT)TO(OUTPUT)LOADCAPACITANCEM INTYPMAXUNITfMAXCL= 15 pF40 MHzCL= 50 pF25tpdRCLKYCL= 15 pF11425nsCLKARCOA11627tPLHCCLRRCOA11220n stenGAL,GAU,GBL,GBUY11628nstdisGAL,GAU,G BL,GBUY1815nstpdRCLKYCL= 50 pF11627nsCLKARCOA11728tPLHCCLRRCOA11321n stenGAL,GAU,GBL,GBUY11830nstdisGAL,GAU,G BL, 5 V, CL= 50 pFPARAMETERMINTYPMAXUNITVOL(P)Quietoutpu t, (V)Quietoutput,minimumdynamicVOL (V)Quietoutput, (mA) Frequency (MHz) VCC = 5-VVCC = 00000001000200030004010001010102 0103 FFFD FFFE FFFF0000 000100000001 0002 00030004010001010102 FFFD FFFE FFFF 0000 0001 Don t AUGUST2004 REVISEDMAY2020 ProductFolderLinks.

9 SN74LV8154 SubmitDocumentationFeedbackCopyright 2004 2020,TexasInstrumentsIncorporatedFigure1 . CLKA,B/ 10; No loadFigure2. ICC vs CLKA,CLKBF requency50% VCCVCCVCC0 V0 VthtsuVOLTAGE WAVEFORMSSETUP AND HOLD TIMESData InputtPLHtPHLtPHLtPLHVOHVOHVOLVOLVCC0 V50% VCC50% VCCI nputOut-of-PhaseOutputIn-PhaseOutputTimi ng Input50% VCCVOLTAGE WAVEFORMSPROPAGATION DELAY TIMESINVERTING AND NONINVERTING OUTPUTSO utputControlOutputWaveform 1S1 at VCC(see Note B)OutputWaveform 2S1 at GND(see Note B)VOLVOHtPZLtPZHtPLZtPHZ VCC0 V50% VCCVOL+ V50% VCC 0 VVCCVOLTAGE WAVEFORMSENABLE AND DISABLE TIMESLOW- AND HIGH-LEVEL ENABLINGtPLH/tPHLtPLZ/tPZLtPHZ/tPZHOpen DrainOpenVCCGNDVCCTESTS1 VCC0 V50% VCCtwVOLTAGE WAVEFORMSPULSE DURATIONI nputNOTES: A.

10 CLincludes probe and jig Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output 2 is for an output with internal conditions such that the output is high, except when disabled by the output All input pulses are supplied by generators having the following characteristics: PRR 1 MHz, ZO= 50 , tr 3 ns, tf 3 The outputs are measured one at a time, with one input transition per tPLZand tPHZare the same as tPZLand tPZHare the same as tPHLand tPLHare the same as All parameters and waveforms are not applicable to all OutputUnder TestCL(see Note A)LOAD CIRCUIT FOR3-STATE AND OPEN-DRAIN OUTPUTSS1 VCCRL= 1 k GNDFrom OutputUnder TestCL(see Note A)TestPointLOAD CIRCUIT FORTOTEM-POLE OUTPUTSOpen50% VCC50% VCC50% VCC50% VCC50% VCC50% VCC50% VCC50% VCCVOH V8SN74LV8154 SCLS589B AUGUST2004.