Stereo PDM-to-I TDM Conversion IC Data Sheet …

1 Stereo PDM-to-I2S or TDM Conversion IC. data Sheet adau7002 . FEATURES GENERAL DESCRIPTION. 64 decimation of a Stereo pulse density modulation (PDM) The adau7002 converts a Stereo PDM bit stream into a PCM. bit stream to pulse code modulation (PCM) audio data output. The source for the PDM data can be two microphones Slave I2S or time division multiplexed (TDM) output interface or other PDM sources. The PCM audio data is output on a Configurable TDM slots serial audio interface port in either I2S or TDM format. I/O supply operation: V to V. The adau7002 is specified over the commercial temperature 64 output sample rate PDM clock range ( 40 C to +85 C). It is available in a halide-free, 8-ball, 64 /128 /192 /256 /384 /512 output sample rate BCLK. mm mm, wafer level chip scale package (WLCSP).

2 Automatic BCLK ratio detection Output sample rate: 4 kHz to 96 kHz Automatic PDM CLK drive at 64 the sample rate Automatic power down with BCLK removal mA operating current at 48 kHz and V IOVDD supply Shutdown current: <1 A. 8-ball, mm mm, mm pitch WLCSP. Power-on reset APPLICATIONS. Mobile computing Portable electronics Consumer electronics FUNCTIONAL BLOCK DIAGRAM. TO CONFIG GND IOVDD. PDM_CLK BCLK. PDM DIGITAL I2S. INPUT DECIMATION OUTPUT LRCLK. PORT FILTERING PORT. PDM_DAT SDATA. 11265-001. adau7002 . Figure 1. Rev. B Document Feedback Information furnished by analog devices is believed to be accurate and reliable. However, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use.

3 Specifications subject to change without notice. No One Technology Way, Box 9106, Norwood, MA 02062-9106, license is granted by implication or otherwise under any patent or patent rights of analog devices . Tel: 2013 2016 analog devices , Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support adau7002 data Sheet TABLE OF CONTENTS. Features .. 1 Pin Configuration and Function Applications .. 1 Typical Performance Characteristics ..6 General Description .. 1 Typical Application Circuit ..8 Functional Block Diagram .. 1 Applications Information ..9 Revision History .. 2 Overview ..9 3 Absolute Maximum 4 Serial Audio Output Interface ..9 Thermal Resistance .. 4 Outline Dimensions .. 13 ESD Caution .. 4 Ordering Guide.

4 13 REVISION HISTORY. 11/2016 Rev. A to Rev. B Added Figure 6; Renumbered Sequentially ..6. Change to Serial Port Timing Section and Time From BCLK Changes to Figure 14 and Figure 15 .. 10. Falling Parameter; Table 7 .. 10 Changes to Figure 16, Figure 17, and Figure 18 .. 11. Changes to Figure 19 Caption and Figure 21 Caption .. 12 Changes to Figure 19, Figure 20, and Figure 21 .. 12. 7/2013 Rev. 0 to Rev. A 1/2013 Revision 0: Initial Version Changes to Supply Current Test 3. Changes to Figure 5 .. 6. Rev. B | Page 2 of 16. data Sheet adau7002 . SPECIFICATIONS. IOVDD = V, TA = 25 C, BCLK = MHz, output = 48 kHz, I2S format, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit DIGITAL INPUT/OUTPUT. High Level Input Voltage (VIH) IOVDD V. Low Level Input Voltage (VIL) IOVDD V.

5 Input Leakage, High (IIH) BCLK and LRCLK pins 1 A. Input Leakage, Low (IIL) BCLK and LRCLK pins 1 A. Input Capacitance 5 pF. SDATA mA. PDM_CLK 9 mA. PERFORMANCE. Dynamic Range 20 Hz to 20 kHz, 60 dB input With A-Weighted Filter (RMS) 110 dB. Signal-to-Noise-Ratio A-weighted, fourth-order input 110 dB. Decimation Ratio 64 . Frequency Response DC to output fS + dB. Stop Band fS. Stop-Band Attenuation 60 dB. Group Delay fS input signal LRCLK cycles Gain PDM to PCM 0 dB. Start-Up Time 48 LRCLK cycles Bit Width Internal and output 20 Bits Interchannel Phase 0 Degrees CLOCKING. Output Sampling Rate fS LRCLK pulse rate 4 48 96 kHz BCLK Frequency fBCLK MHz POWER SUPPLIES. Supply Voltage Range IOVDD V. Supply Current IOVDD = V mA. IOVDD = V mA. IOVDD = V, 16 kHz output mA. IOVDD = V, 16 kHz output mA.

6 Shutdown Current IOVDDSD, no input clocks 1 A. Rev. B | Page 3 of 16. adau7002 data Sheet ABSOLUTE MAXIMUM RATINGS. Absolute maximum ratings apply at 25 C, unless otherwise noted. THERMAL RESISTANCE. Table 2. JA (junction to air) is specified for the worst-case conditions, Parameter Rating that is, a device soldered in a circuit board for surface-mount packages. JA is determined according to JESD51-9 on a 4-layer IOVDD Supply Voltage V. printed circuit board (PCB) with natural convection cooling. Input Voltage V. ESD Susceptibility 4 kV Table 3. Thermal Resistance Storage Temperature Range 65 C to +150 C Package Type JA Unit Operating Temperature Range 40 C to +85 C 8-ball, mm mm WLCSP 90 C/W. Junction Temperature Range 65 C to +165 C. Lead Temperature (Soldering, 60 sec) 300 C.

7 ESD CAUTION. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. B | Page 4 of 16. data Sheet adau7002 . PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. BALL A1. CORNER. 1 2. A PDM_ PDM_. DAT CLK. B SDATA BCLK. C GND LRCLK. D. 11265-002. IOVDD CONFIG. TOP VIEW. (BALL SIDE DOWN). Figure 2. Pin Configuration (Top Side View). Table 4. Pin Function Descriptions Pin No. Mnemonic Type Description A1 PDM_DAT Input PDM data Input A2 PDM_CLK Output PDM Clock Output B1 SDATA Output Serial data Output for I2S/TDM.

8 B2 BCLK Input Bit Clock for I2S/TDM. C1 GND Ground Ground C2 LRCLK Input Left/Right Clock for I2S/Frame Sync for TDM. D1 IOVDD Supply Input/Output and Digital Supply D2 CONFIG Input Configuration Pin Rev. B | Page 5 of 16. adau7002 data Sheet TYPICAL PERFORMANCE CHARACTERISTICS. 0 160. 10. 20 140. 30. 40. 50 120. 60. GROUP DELAY ( s). 70 100. LEVEL (dBFS). 80. 90. 80. 100. 110. 120 60. CH1. 130 CH2. 140 40. 150. 160. 20. 170. 180. 190 0. 11265-101. 11265-003. 20 100 1k 10k 20k 10 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz). Figure 3. FFT, fS = 48 kHz, 60 dBFS Input Figure 6. Group Delay vs. Frequency, fS = 48 kHz 0. 20. 0. 40. THD + N (dBFS). LEVEL (dBFS). 60. 80. 100. 120. 140. 11265-004. 11265-006. 1 1. NORMALIZED FREQUENCY (RELATIVE TO fS) (Hz) NORMALIZED FREQUENCY (RELATIVE TO fS) (Hz).

9 Figure 4. Frequency Response Figure 7. Total Harmonic Distortion + Noise (THD + N) vs. Normalized Frequency (Relative to fS). 8 0. 7. 20. GROUP DELAY (LRCLK CYCLES). 6. THD + N LEVEL (dBFS). 40. 5. 4 60. 3. 80. 2. 100. 1. 0 120. 11265-100. 1. 11265-007. 120 100 80 60 40 20 0. NORMALIZED FREQUENCY (RELATIVE TO fS) (Hz) GENERATOR LEVEL (dBFS). Figure 5. Group Delay vs. Normalized Frequency (Relative to fS) Figure 8. THD + N Level vs. Generator Level Rev. B | Page 6 of 16. data Sheet adau7002 . SUPPLY CURRENT (mA). 11265-009. SUPPLY VOLTAGE (V). Figure 9. Supply Current vs. Supply Voltage 0. 20. 40. 60. MAGNITUDE (dB). 80. 100. 120. 140. 160. 11265-010. 0 FREQUENCY (MHz). Figure 10. Out-of-Band Frequency Response (48 kHz Output). Rev. B | Page 7 of 16. adau7002 data Sheet TYPICAL APPLICATION CIRCUIT.

10 IOVDD. F. IOVDD. PDM_CLK PDM_CLK LRCLK LRCLK. PDM_DAT PDM_DAT BCLK BCLK. adau7002 . CONFIG CONFIG SDATA SDATA. GND. OPTIONAL. PULL-DOWN. RESISTOR. 11265-011. Figure 11. Typical Application Circuit Rev. B | Page 8 of 16. data Sheet adau7002 . APPLICATIONS INFORMATION. OVERVIEW Table 5. PDM Timing Parameters The adau7002 provides Stereo decimation from a 1-bit PDM Parameter tMIN tMAX Unit source to a 20-bit PCM audio. The downsampling ratio is fixed data Setup Time, tSETUP 10 ns at 64 . The 20-bit downsampled PCM audio is output via data Hold Time, tHOLD 7 ns standard I2S or TDM formats. PDM data is latched on both edges of the clock. The input source for the adau7002 can be any device that has a PDM output, such as a digital microphone. The output pins of PDM_CLK. these microphones can connect directly to the input pins of the adau7002 .