Synchronizing Multiple AD9852 DDS-Based …

1 REV. 0aAN-605 APPLICATION NOTEOne Technology Way Box 9106 Norwood, MA 02062-9106 Tel: 781/329-4700 Fax: 781/326-8703 2003 analog Devices, Multiple AD9852 DDS-Based Synthesizersby David BrandonINTRODUCTIONMany applications require the generation of two ormore sinusoidal or square wave signals with a knownphase relationship between them. The AD9852 DDS ICfrom analog Devices is capable of providing such sig-nals. This application note offers detailed instructionson how to synchronize two or more of these devices andconsiders possible sources of phase error.

2 For a quadra-ture application, see the AD9854 DDS with its built-inquadrature configuration; however, this applicationnote would also apply to the AD9854 as successful synchronization, the user must have con-trol over the timing relationship between REFCLK andthe rising edge of the EXT I/O UPDATE CLK. The goal isto have all DDSs operating on the same SYSTEM CLKcount and not off by 1 or more counts from each , the EXT I/O UPDATE CLK must be made syn-chronous with the phase errors due to DAC output filtering mis-matches, the AD9852 features programmable phaseadjust that can null out these types of CLOCKThe first requirement for successful synchronization ofmultiple AD9852s is that there must be minimal phaseerror between the REFCLK inputs to all DDSs.

3 Any differ-ence in-phase between the REFCLK edges will result in aproportional phase difference at the DDS , the user must employ a careful clock distribu-tion practice in the layout of the PCB (see Figure 1).The AD9852 REFCLK input circuitry has an option ofusing differential inputs or a single-ended REFCLK mode is recommended for its opti-mum switching characteristics. The REFCLK edgesshould have minimum input jitter and fast rise/fall times(less than 1 ns is recommended). A slow rise time onREFCLK can increase the phase error time because thevoltage trip point of the input circuit varies fromdevice to NO.

4 1 DDS NO. 2 DDS NO. 3 REFCLKDDS NO. 2 DDS NO. 3A = B = CABCOPTIMUM LAYOUTF igure 1. REFCLK DistributionI/O UPDATE CLOCKThe I/O UPDATE CLK is responsible for transferring thecontents of the I/O port buffer to the programmingregisters where the data becomes active. This clockhas two modes of operation in which the DDS cansupply the I/O UPDATE CLK, or the user can supply synchronization reasons, external mode is highlyrecommended. Internal mode was not given consider-ation for complexity I/O INTERFACE DETAILSOnce a fast-edged and properly routed REFCLK signal isprovided, the next timing requirement is the coincidenttransfer of the data into the DDS programming I/O UPDATE CLK transfers the contents of the I/Oport buffer to the programming registers where databecomes active.

5 Synchronization of Multiple DDSsrequires that the EXT I/O UPDATE CLK s rising edgeoccur simultaneously at all DDSs, just like the addition, the rising edge of the EXT I/O UPDATE CLKmust occur at the proper time with respect to REFCLK. 2 AN-605 REV. 0 The AD9852 can be programmed in serial or parallelmode. Figure 2 depicts the parallel mode. If shown, theserial mode would display an additional 7-bit shift regis-ter and other support circuitry in front of the paralleldata path. However, the main reason for showing thisdiagram is to view the paths of REFCLK and EXT I/OUPDATE few things to note in Figure 2 are how the SYSTEMCLK is derived and the inversion of REFCLK in single-ended REFCLK mode.

6 Also note, an asynchronous EXTI/O UPDATE CLK will be made synchronous to the SYSTEMCLK via the edge detection circuitry (see Figure 3). How-ever, it is incumbent upon the user to make itsynchronous with the REFCLK to avoid a SYSTEM CLKcount mismatch between on the setting of the REFCLK mode (single-ended or differential) and/or the use of the on-chipREFCLK multiplier (PLL), the timing relationshipbetween REFCLK and EXT I/O UPDATE CLK will timing changes will be addressed UPDATECLOCKUPDATE REGS(SEE TIMING FOREDGE DETECT BELOW)

7 1 OF 40 LATCHDENREADBACKMUXDECODEDDSPROGRAMMINGR EGISTERSI/O PORT BUFFERSSYSTEM CLOCKF/FDQCK1 OF 406401 OF 408886 ADDRESSDATAADDRESSWR888320 RDFigure 2. AD9852 Parallel Interface Block Diagram0123 SYSTEM CLKEXT I/O UPDATE CLKUPDATE REGSFIRST SYSTEM TO SEEEXT I/O UPDATE CLKFORMS RISING EDGEOF UPDATE REGSI/O PORT BUFFERS CONTENTSARE REGISTERED INTOPROGRAMMING REGISTERSFORMS FALLING EDGEOF UPDATE REGSF igure 3. Ext I/O Update CLK's Edge Detect Timing 3 AN-605 REV. 0 From the timing in Figure 3, it is essential that a propertime relationship exist between EXT I/O UPDATE CLKand the SYSTEM CLOCK for synchronization to occur.

8 Ifthis time relationship is met, then all SYSTEM CLOCK sare on the same count across all DDSs and not off by 1or more SYSTEM CLOCK counts. The user would controlthis relationship with the control of the rising edge of theEXT I/O UPDATE CLK with respect to the REFCLK. Thistiming relationship will be addressed in the SYNCHRO-NIZATION INSTRUCTIONS BACKGROUNDA RESET must be given after power-up and priorto transferring any data to the DDS. This places theDDS output into a known phase, which becomes thecommon reference point that allows the synchronizationof Multiple forces the AD9852 s phase accumulator state tobecome COS(0).

9 When new data is sent simultaneouslyto Multiple DDSs, a coherent phase relationship can bemaintained, or the relative phase offset betweenmultiple DDSs can be predictability shifted by means ofthe phase offset adjustment register. The AD9852 has14 bits of phase-offset adjustment that amounts toa phase resolution of . The phase-offset feature islocated between the phase accumulator and the phase-to-amplitude INSTRUCTIONSF igure 4 presents one possible reference design forthe successful synchronization of Multiple DDSs.

10 Thisexample shows how to place two DDSs into the samephase Figure 4, the D flip-flop enables the EXT I/O UPDATECLK to be synchronous with the REFCLK and provides asetup time. Proper operation may require additionaltime delay in the REFCLK path. This delaydepends on the CK to Q propagation time of the flip-flop. The recommended timing relationship between theEXT I/O UPDATE CLK (Pin 20) and the REFCLK (Pin 69) isdepicted in Figures 5 and 6, depending on single-endedor differential REFCLK mode. Timing for the REFCLK multiplier enabled is depicted in Figures 8 and are some general instructions and recommenda-tions for placing two DDSs into the same phaserelationship (refer to Figure 4).