Ultra Low Input Bias Current Instrumentation …

1 1994 Burr-Brown CorporationPDS-1242 BPrinted in May, 1995 Difet ; Burr-Brown CorporationFEATURESlLOW Input bias Current : 3fA typlBUFFERED GUARD DRIVE PINSlLOW OFFSET VOLTAGE: 2mV maxlHIGH COMMON-MODE REJECTION:84dB (G = 10)lLOW QUIESCENT Current : 1mAlINPUT OVER-VOLTAGE PROTECTION: 40 VAPPLICATIONSlLABORATORY INSTRUMENTATIONlpH MEASUREMENTlION SPECIFIC PROBESlLEAKAGE Current MEASUREMENTU ltra Low Input bias CurrentINSTRUMENTATION AMPLIFIERINA116 INA116 INA116A1A2A360k 60k 60k 60k VINVINRGV+V INA116 VORefG = 1 +50k RG +25k 25k GuardGuardGuardGuard+1+1 Over-VoltageProtectionOver-VoltageProtec tion234116567811913 DESCRIPTIONThe INA116 is a complete monolithic FET- Input instru-mentation amplifier with extremely low Input biascurrent. Difet inputs and special guarding techniquesyield Input bias currents of 3fA at 25 C, and only 25fAat 85 C. Its 3-op amp topology allows gains to be setfrom 1 to 1000 by connecting a single external pins adjacent to both Input connections can beused to drive circuit board and Input cable guards tomaintain extremely low Input bias INA116 is available in 16-pin plastic DIP and SOL-16surface-mount packages, specified for the 40 C to +85 Ctemperature Airport Industrial Park Mailing Address: PO Box 11400, Tucson, AZ 85734 Street Address: 6730 S.

2 Tucson Blvd., Tucson, AZ 85706 Tel: (520) 746-1111 Twx: 910-952-1111 Internet: FAXLine: (800) 548-6133 (US/Canada Only) Cable: BBRCORP Telex: 066-6491 FAX: (520) 889-1510 Immediate Product Info: (800) 548-6132 SBOS034 INA1162 SPECIFICATIONSAT TA = +25 C, VS = 15V, RL = 10k , unless otherwise , UINA116PA, UAPARAMETERCONDITIONSMINTYPMAXMINTYPMAXU NITSINPUTO ffset Voltage, RTII nitialTA = +25 C 2 2/G[ 5 5/GmV vs TemperatureTA = TMIN to TMAXSee Typical Curve[ vs Power SupplyVS = to 18V 10 15/G 50 100/G[ 100 200/G V/VLong-Term Stability 1 5/G[ V/moBias Current 3 25[ 100fAvs TemperatureSee Typical Curve[Offset Current 1 25[ 100fAvs TemperatureSee Typical Curve[Impedance, Differential>1015 [ /pFCommon-Mode>1015/7[ /pFCommon-Mode Voltage Range(V+) 4(V+) 2[[V(V )+4(V )+ [[VSafe Input Voltage 40[VCommon-Mode RejectionVCM = 11V, RS = 1k G = 1808973[dBG = 10849278[dBG = 100869480[dBVCM = 5V, G = 1000869480[dBNOISEV oltage Noise, RTIG = 1000, RS = 0 f = 1kHz28[nV/ HzfB = to 10Hz2[ Vp-pCurrent Noisef = [fA/ HzGAINGain Equation1+(50k /RG)]]]]]]]]]]]]]]]]]]]]]]

3 [V/VRange of Gain11000[[V/VGain ErrorG = 1 [ = 10 [ = 100 [ = 1000 [%Gain vs Temperature(1)G = 1 5 10[ 20ppm/ C50k Resistance(1)(2) 25 100[ 100ppm/ C NonlinearityG = 1 [ of FSRG = 10 [ of FSRG = 100 [ of FSRG = 1000 [% of FSRGUARD OUTPUTSO ffset Voltage 15 50[[mVOutput Impedance650[ Current Drive+2/ [mAOUTPUTV oltage PositiveRL = 10k (V+) 1(V+) [[VNegativeRL = 10k (V ) + (V ) + [[VLoad Capacitance Stability1000[pFShort-Circuit Current +5/ 12[mAFREQUENCY RESPONSEB andwidth, 3dBG = 1800[kHzG = 10500[kHzG = 10070[kHzG = 10007[kHzSlew RateG = 10 to [V/ sSettling Time, Step, G = 122[ sG = 1025[ sG = 100145[ sG = 1000400[ sOutput Overload Recovery50% Overdrive20[ sPOWER SUPPLYV oltage Range 15 18[[[VCurrentVIN = 0V 1 [[mATEMPERATURE RANGES pecification 4085[[ COperating 40125[[ C JA80[ C/W[ Specification same as INA116 PNOTE: (1) Guaranteed by wafer test. (2) Temperature coefficient of the 50k term in the gain equation.]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]] ]]]]]]]]]]]]]

4 3 INA116 The information provided herein is believed to be reliable; however, BURR-BROWN assumes no responsibility for inaccuracies or omissions. BURR-BROWN assumesno responsibility for the use of this information, and all use of such information shall be entirely at the user s own risk. Prices and specifications are subject to changewithout notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. BURR-BROWN does not authorize or warrantany BURR-BROWN product for use in life support devices and/or ViewDIPSOL-16 Supply Voltage .. 18 VInput Voltage Range .. 40 VOutput Short-Circuit (to ground) .. ContinuousOperating Temperature .. 40 C to +125 CStorage Temperature .. 40 C to +125 CJunction Temperature .. +150 CLead Temperature (soldering, 10s) .. +300 CABSOLUTE MAXIMUM RATINGSRGG uard VING uard NC: No Internal +1234 Guard +VING uard +V 567816151413 NCVONCRef1211109 +ELECTROSTATICDISCHARGE SENSITIVITYThis integrated circuit can be damaged by ESD.

5 Burr-Brownrecommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handlingand installation procedures can cause damage can range from subtle performance degradationto complete device failure. Precision integrated circuits maybe more susceptible to damage because very small parametricchanges could cause the device not to meet its INFORMATIONPACKAGE DRAWINGPRODUCTPACKAGENUMBER(1)INA116PA16 -Pin Plastic DIP180 INA116P16-Pin Plastic DIP180 INA116 UASOL-16 Surface-Mount211 INA116 USOL-16 Surface-Mount211 NOTE: (1) For detailed drawing and dimension table, please see end of datasheet, or Appendix C of Burr-Brown IC Data CONFIGURATION INA1164 TYPICAL PERFORMANCE CURVESAt TA = +25 C, VS = 15V, RL = 10k , unless otherwise vs FREQUENCY6050403020100 10 20 Gain (dB)Frequency (Hz)1k10k100k1M10MG = 100G = 10G = 1G = 1000 COMMON-MODE REJECTION vs FREQUENCY1009080706050403020100 Common-Mode Rejection (dB)Frequency (Hz)101001k10k100kG = 1000V/VG = 100V/VG = 10V/VG = 1V/VPOSITIVE POWER SUPPLY REJECTIONvs FREQUENCYF requency (Hz)Power Supply Rejection (dB)1201008060402001101001k10k100kG = 1000V/VG = 100V/VG = 1V/VG = 10V/VNEGATIVE POWER SUPPLY REJECTIONvs FREQUENCYF requency (Hz)Power Supply Rejection (dB)1201008060402001101001k10k100kG = 1G = 1kG = 10 < 100 Input bias Current vs Input VOLTAGEI nput Voltage (V) Input bias Current (fA)151050 5 10 15 15 10 5051015 Input bias Current vs TEMPERATUREI nput bias Current (fA)

6 1000100101 75 50 250255075100125 IBMeasurement LimitIOS 5 INA116 Input OFFSET VOLTAGE DRIFTPRODUCTION DISTRIBUTIONP roduction Distribution (%)Offset Voltage Drift ( V/ C)TYPICAL PERFORMANCE CURVES (CONT)At TA = +25 C, VS = 15V, RL = 10k , unless otherwise OVER-VOLTAGE V/I CHARACTERISTICS43210 1 2 3 4 Input Current (mA) Input Voltage (V) 40 30 20 10010203040G = 1000V/VG = 1000V/VG = 1V/VG = 1V/VINPUT REFERRED NOISE vs FREQUENCYF requency (Hz)Voltage Noise Density (nV/ Hz)1101k10010k1k1001010kG = 1V/VG = 10V/VG = 1000V/VBandwidth LimitINPUT COMMON-MODE RANGEvs OUTPUT VOLTAGEO utput Voltage (V)Common-Mode Voltage (V) 15 100515 5151050 5 10 1510G 10G 10G = 1G = 1VD/2 + +VCMVOVD/2 INA116 Ref 15V+15VG = 1G = 1 OFFSET VOLTAGE WARM-UP151050 5 10 15G = 1G = 1 Offset Voltage Change ( V)Time After Power Supply Turn-On (s)0510152025G 10G 10 QUIESCENT Current AND SLEW RATEvs TEMPERATURET emperature ( C)Quiescent Current ( A) Rate (V/ s) 75 50 = 100G = 10G = 10 80 60 40 20 INA1166G=1G=10G=100G=1000G=1G=10G=100G=1 00020mV/div100 s/div20mV/div10 s/div5V/div100 s/div5V/div100 s/divLARGE SIGNAL RESPONSELARGE SIGNAL RESPONSESMALL SIGNAL RESPONSESMALL SIGNAL RESPONSEMAXIMUM OUTPUT VOLTAGE vs FREQUENCY3228242016128401001k10k100k1 MFrequency (Hz)Peak-to-Peak Output Voltage (V)G = 10, 100G = 1G = 1000 TYPICAL PERFORMANCE CURVES (CONT)At TA = +25 C, VS = 15V, RL = 10k , unless otherwise NOISE, TO 10 HzINPUT-REFERRED, G 100500nV/div 7 INA116 APPLICATIONS INFORMATIONF igure 1 shows the connections required for basic operationof the INA116.

7 Applications with noisy or high impedancepower supplies may require decoupling capacitors close tothe supply pins as output is referred to the output reference (Ref) terminalwhich is normally grounded. This must be a low impedanceconnection to assure good common-mode rejection. A resis-tance of 30 in series with this connection will cause atypical device to degrade to approximately 72dB CMR atG = THE GAINGain of the INA116 is set by connecting a single externalresistor, RG, as shown. The gain is Commonly used gains and resistor values are shown inFigure 50k term in equation 1 is the sum of the two feedbackresistors of A1 and A2. These on-chip metal film resistors arelaser trimmed to accurate absolute values. The accuracy andtemperature coefficient of these resistors are included in thegain accuracy and drift specifications of the stability and temperature drift of RG also affect s contribution to gain accuracy and drift can be directlyinferred from the gain equation (1).

8 Low resistor valuesrequired for high gain make wiring resistance add to the wiring resistance that will contributeadditional gain error in gains of approximately 100 TRIMMINGThe INA116 is laser trimmed for low offset voltage andoffset voltage drift; most applications require no externaloffset adjustment. Figure 2 shows an optional circuit fortrimming the output offset voltage. A voltage applied to theRef terminal is summed at the output. Op amp A1 providesa low source impedance for the Ref terminal, assuring goodcommon-mode +50 k RG(1)FIGURE 1. Basic drawn in simplified form:VORefVIN VIN+A1A2A3R460k R360k R260k R160k VINVINRGV INA116 VORefG = 1 +50k RG +RFB25k RFB25k +1+1 Over-VoltageProtectionOver-VoltageProtec tion432116567811913 Input GuardsSee FV+ FDESIREDGAIN1251020501002005001000200050 0010000NC: No ( ) 1% RG( ) INA1168 FIGURE 2. Optional Trimming of Output Offset bias Current RETURN PATHI nput circuitry must provide an Input bias Current path forproper operation.

9 Figure 3 shows resistors R1 and R2 toprovide an Input Current path. Without these resistors, theinputs would eventually float to a potential that exceeds thecommon-mode range of the INA116 and the Input amplifierswould saturate. Because of its exceedingly low Input biascurrent, improperly biased inputs may operate normally fora period of time after power is first applied, or BOARD LAYOUT AND ASSEMBLYC areful circuit board layout and assembly techniques arerequired to achieve the exceptionally low Input bias currentperformance of the INA116. Guard terminals adjacent toboth inputs make it easy to properly guard the critical inputterminal layout. Since traces are not required to run betweendevice pins, this layout is easily accomplished, even with thesurface mount package. The guards should completely en-circle their respective Input connections see Figure 4. Bothsides of the circuit board should be guarded, even if only oneside has an Input terminal conductor.

10 Route any time-varying signals away from the Input terminals. Solder maskshould not cover the Input and guard traces since this canincrease 3. Providing An Input bias Current 4. Circuit Board Guard assembly, the circuit board should be cleaned. Com-mercial solvents should be chosen according to the solderingmethod and flux used. Solvents should be cleaned andreplaced often. Solvent cleaning should be followed by a de-ionized water rinse and 85 C bake can be used, but select and evaluate them carefullyfor best results. Use caution when installing the INA116 ina socket. Careless handling can contaminate the plastic nearthe Input pins, dramatically increasing leakage proven low leakage Current assembly method is to bendthe Input pins outward so they do not contact the circuitboard. Input connections are made in air and soldereddirectly to the Input pin. This technique is often not practicalor production-worthy.