AD9910 (Rev. E) - Analog Devices
I/O_UPDATE Pulse Width High >1 SYNC_CLK cycle Minimum Profile Toggle Period 2 SYNC_CLK cycles TxENABLE and 16-BIT PARALLEL (DATA) BUS TIMING . Maximum PDCLK Frequency . 250 . MHz . TxENABLE/Data Setup Time (to PDCLK) 1.75 . ns . TxENABLE/Data Hold Time (to PDCLK) 0 . ns . MISCELLANEOUS TIMING CHARACTERISTICS . Wake-Up …
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