AD9910 (Rev. E) - Analog Devices
Minimum SCLK Clock Pulse Width . Low : 4 . ns . High . 4 . ns . Maximum SCLK Rise/Fall Time 2 ns Minimum Data Setup Time to SCLK . 5 . ns . Minimum Data Hold Time to SCLK . 0 . ns . Maximum Data Valid Time in Read Mode . 11 . ns : I/O_UPDATE/PROFILE[2:0] TIMING CHARACTERISTICS . Minimum Setup Time to SYNC_CL K 1.75 . ns Minimum Hold Time to ...
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