DESIGNING COMBINATIONAL LOGIC GATES IN CMOS
Figure 6.5 shows atwo-input NAND gate F = A·B(). The PDN network consists of two NMOS devices in series that conduct when both A and B are high. The PUN is the dual net-work, and consists of two parallel PMOS transistors. This means that F is 1 if A = 0 or B = 0, which is equivalent to F = A·B. The truth table for the simple two input NAND ...
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