MT-016: Basic DAC Architectures III: Segmented DACs
latches are required to implement this ultra low glitch architecture. The basic current switching cell in the TxDAC family is made up of a differential PMOS transistor pair as shown in Figure 6. The differential pairs are driven with low-level logic to minimize switching transients and time skew. The DAC outputs are symmetrical differential
Architecture, Basics, Adcs, Segmented, Glitch, Low glitch, Basic dac architectures iii, Segmented dacs
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