1 ppm, 20-Bit, ±1 LSB INL, Voltage Output DAC

1 1 ppm, 20-Bit, 1 LSB INL, Voltage Output DAC. Data Sheet AD5791. FEATURES FUNCTIONAL BLOCK DIAGRAM. VCC VDD VREFPF VREFPS. 1 ppm resolution 1 ppm INL. AD5791 . nV/ Hz noise spectral density IOVCC A1 RFB. R1 RFB. LSB long-term linearity stability INV. SDIN. < ppm/ C temperature drift INPUT. SHIFT 20. DAC. 20 20-BIT. SCLK VOUT. 1 s settling time SYNC. REGISTER. AND. REG DAC. CONTROL. nV-sec glitch impulse SDO LOGIC. Operating temperature range: 40 C to +125 C 6k . LDAC. 20-lead TSSOP package Wide power supply range up to V CLR POWER-ON-RESET. RESET AND CLEAR LOGIC. 35 MHz Schmitt triggered digital interface 08964-001. V compatible digital interface DGND VSS AGND VREFNF VREFNS. APPLICATIONS Figure 1. Medical instrumentation Table 1. Complementary Devices Test and measurement Model Description Industrial control AD8675 Ultra precision, 36 V, nV/ Hz rail-to-rail High end scientific and aerospace instrumentation Output op amp AD8676 Ultra precision, 36 V, nV/ Hz dual rail-to- rail Output op amp ADA4898-1 High Voltage , low noise, low distortion, unity-gain stable, high speed op amp Table 2.

2 Related Device Model Description AD5781 18-bit, LSB INL, Voltage Output DAC. GENERAL DESCRIPTION. The AD57911 is a single 20-bit, unbuffered Voltage - Output digital - Output powers up to 0 V and in a known Output impedance to- analog converter (DAC) that operates from a bipolar supply of state and remains in this state until a valid write to the device up to 33 V. The AD5791 accepts a positive reference input in the takes place. The device provides an Output clamp feature that range 5 V to VDD V and a negative reference input in the places the Output in a defined load state. range VSS + V to 0 V. The AD5791 offers a relative accuracy PRODUCT HIGHLIGHTS. specification of 1 LSB max, and operation is guaranteed monotonic with a 1 LSB differential nonlinearity (DNL) 1. 1 ppm Accuracy. maximum specification. 2. Wide Power Supply Range up to V. 3. Operating Temperature Range: 40 C to +125 C.

3 The device uses a versatile 3-wire serial interface that operates 4. Low nV/ Hz Noise Spectral Density. at clock rates up to 35 MHz and that is compatible with 5. Low ppm/ C Temperature Drift. standard serial peripheral interface (SPI), QSPI , MICROWIRE , and DSP interface standards. The device incorporates a power-on reset circuit that ensures the DAC. 1. Protected by Patent No. 7,884,747. Other patents pending. Rev. F Document Feedback Information furnished by analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, Box 9106, Norwood, MA 02062-9106, license is granted by implication or otherwise under any patent or patent rights of analog Devices.

4 Tel: 2010 2020 analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support AD5791 Data Sheet TABLE OF CONTENTS. Features .. 1 Serial Interface .. 19. Applications .. 1 Hardware Control Pins .. 20. Functional Block Diagram .. 1 On-Chip Registers .. 21. General Description .. 1 AD5791 Features .. 24. Product Highlights .. 1 Power-On to 0 24. Revision History .. 2 Power-Up Sequence .. 24. 3 Configuring the AD5791 .. 24. Timing Characteristics .. 5 DAC Output State .. 24. Absolute Maximum 7 Linearity Compensation .. 24. ESD Caution .. 7 Output Amplifier 24. Pin Configuration and Function Descriptions .. 8 Applications Information .. 26. Typical Performance Characteristics .. 9 Typical Operating Circuit .. 26. Terminology .. 17 Outline Dimensions .. 27. Theory of Operation .. 19 Ordering Guide .. 27. DAC Architecture.

5 19. REVISION HISTORY. 1/2020 Rev. E to Rev. F 9/2011 Rev. A to Rev. B. Change to Endnote 2, Table 4 .. 5 Added Patent Note ..1. Change to Input Shift Register Section .. 19 Changes to Table Changes to OPGND Description Column, Table 12 .. 23. 4/2018 Rev. D to Rev. E Change to Figure 51 .. 25. Change to Figure 49 .. 19. Added Power-Up Sequence Section and Figure 50; Renumbered 8/2011 Rev. 0 to Rev. A. Sequentially .. 24 Change to Features Section ..1. Changes to Specifications Section, Table 3 ..3. 7/2013 Rev. C to Rev. D Deleted t14 Timing Specification in Table 4, Renumbered Change to Table 4 .. 5 Subsequent Timing Parameters Sequentially ..5. Deleted Figure 4, Renumbered 7 Changes to Figure 2 and Figure 3 ..6. Deleted Daisy-Chain Operation Section and Figure 51 .. 21 Changes to Figure 4 ..7. Changes to Figure 16. 11/2011 Rev. B to Rev. C Changes to Figure 16. Added Figure 48; Renumbered Sequentially.

6 17 Added Figure 44, Figure 45, and Figure 46, Renumbered Change to Ideal Transfer Function 22 Sequentially .. 16. 7/2010 Revision 0: Initial Version Rev. F | Page 2 of 27. Data Sheet AD5791. SPECIFICATIONS. VDD = V to V, VSS = V to V, VREFP = 10 V, VREFN = 10 V, VCC = V to + V, IOVCC = V to V, RL = unloaded, CL = unloaded, all specifications TMIN to TMAX, unless otherwise noted. Table 3. A, B Version 1. Parameter Min Typ Max Unit Test Conditions/Comments STATIC PERFORMANCE 2. Resolution 20 Bits Integral Nonlinearity Error (Relative Accuracy) 1 +1 LSB B version, VREFP = +10 V, VREFN = 10 V, TA = 0 C to 105 C. + LSB B version, VREFP = +10 V, VREFN = 10 V. + LSB B version, VREFP = 10 V, VREFN = 0 V 3. 3 1 +3 LSB B version, VREFP = 5 V, VREFN = 0 V3. 4 2 +4 LSB A version 4. Differential Nonlinearity Error 1 +1 LSB VREFP = +10 V, VREFN = 10 V. + LSB VREFP = 10 V, VREFN = 0 V. 1 + LSB VREFP = 5 V, VREFN = 0 V.

7 Linearity Error Long Term Stability 5 LSB After 500 hours at TA = 125 C. LSB After 1000 hours at TA = 125 C. LSB After 1000 hours at TA = 100 C. Full-Scale Error 7 +7 LSB VREFP = +10 V, VREFN = 10 V3. 11 +11 LSB VREFP = 10 V, VREFN = 0 V3. 21 +21 LSB VREFP = 5 V, VREFN = 0 V3. 4 +4 LSB VREFP = +10 V, VREFN = 10 V3, TA = 0 C to 105 C. 4 +4 LSB VREFP = 10 V, VREFN = 0 V3, TA = 0 C to 105 C. 6 +6 LSB VREFP = 5 V, VREFN = 0 V3, TA = 0 C to 105 C. Full-Scale Error Temperature Coefficient ppm FSR/ C. Zero-Scale Error 7 +7 LSB VREFP = +10 V, VREFN = 10 V3. 10 +10 LSB VREFP = 10 V, VREFN = 0 V3. 21 +21 LSB VREFP = 5 V, VREFN = 0 V3. 4 +4 LSB VREFP = +10 V, VREFN = 10 V3, TA = 0 C to 105 C. 4 +4 LSB VREFP = 10 V, VREFN = 0 V3, TA = 0 C to 105 C. 6 +6 LSB VREFP = 5 V, VREFN = 0 V3, TA = 0 C to 105 C. Zero-Scale Error Temperature Coefficient3 ppm FSR/ C. Gain Error 6 +6 ppm FSR VREFP = +10 V, VREFN = 10 V3.

8 10 +10 ppm FSR VREFP = 10 V, VREFN = 0 V3. 20 +20 ppm FSR VREFP = 5 V, VREFN = 0 V3. 6 +6 ppm FSR VREFP = +10 V, VREFN = 10 V3, TA = 0 C to 105 C. 6 +6 ppm FSR VREFP = 10 V, VREFN = 0 V3, TA = 0 C to 105 C. 7 +7 ppm FSR VREFP = 5 V, VREFN = 0 V3, TA = 0 C to 105 C. Gain Error Temperature Coefficient3 ppm FSR/ C. R1, RFB Matching %. Output CHARACTERISTICS3. Output Voltage Range VREFN VREFP V. Output Slew Rate 50 V/ s Output Voltage Settling Time 1 s 10 V step to , using the AD845 buffer in unity-gain mode 1 s 500 code step to 1 LSB6. Output Noise Spectral Density nV/ Hz at 1 kHz, DAC code = midscale nV/ Hz at 10 kHz, DAC code = midscale nV/ Hz At 100 kHz, DAC code = midscale Output Voltage Noise V p-p DAC code = midscale, Hz to 10 Hz bandwidth 7. Rev. F | Page 3 of 27. AD5791 Data Sheet A, B Version 1. Parameter Min Typ Max Unit Test Conditions/Comments Midscale Glitch Impulse 8 nV-sec VREFP = +10 V, VREFN = 10 V.

9 NV-sec VREFP = 10 V, VREFN = 0 V. nV-sec VREFP = 5 V, VREFN = 0 V. MSB Segment Glitch Impulse8 nV-sec VREFP = +10 V, VREFN = 10 V, see Figure 42. nV-sec VREFP = 10 V, VREFN = 0 V, see Figure 43. nV-sec VREFP = 5 V, VREFN = 0 V, see Figure 44. Output Enabled Glitch Impulse 45 nV-sec On removal of Output ground clamp digital Feedthrough nV-sec DC Output Impedance (Normal Mode) k . DC Output Impedance ( Output Clamped 6 k . to Ground). Spurious Free Dynamic Range 100 dB 1 kHz tone, 10 kHz sample rate Total Harmonic Distortion 97 dB 1 kHz tone, 10 kHz sample rate REFERENCE INPUTS3. VREFP Input Range 5 VDD V V. VREFN Input Range VSS + V 0. DC Input Impedance 5 k VREFP, VREFN, code dependent, typical at midscale code Input Capacitance 15 pF VREFP, VREFN. LOGIC INPUTS3. Input Current 9 1 +1 A. Input Low Voltage , VIL IOVCC V IOVCC = V to V. Input High Voltage , VIH IOVCC V IOVCC = V to V. Pin Capacitance 5 pF.

10 LOGIC Output (SDO)3. Output Low Voltage , VOL V IOVCC = V to V, sinking 1 mA. Output High Voltage , VOH IOVCC V V IOVCC = V to V, sourcing 1 mA. High Impedance Leakage Current 1 A. High Impedance Output Capacitance 3 pF. POWER REQUIREMENTS All digital inputs at DGND or IOVCC. VDD VSS + 33 V. VSS VDD 33 V. VCC V. IOVCC V IOVCC VCC. IDD mA. ISS 4 mA. ICC 600 900 A. IOICC 52 140 A SDO disabled DC Power Supply Rejection Ratio3, 10 V/V VDD 10%, VSS = 15 V. V/V VSS 10%, VDD = 15 V. AC Power Supply Rejection Ratio3 95 dB VDD 200 mV, 50 Hz/60 Hz, VSS = 15 V. 95 dB VSS 200 mV, 50 Hz/60 Hz, VDD = 15 V. 1. Temperature range: 40 C to +125 C, typical at +25 C and VDD = +15 V, VSS = 15 V, VREFP = +10 V, VREFN = 10 V. 2. Performance characterized with AD8676 BRZ Voltage reference buffers and AD8675 ARZ Output buffer. 3. Guaranteed by design and characterization, not production tested. 4. Valid for all Voltage reference spans.