11.3 Gbps, 12 × 12 Digital Crosspoint Switch Data …

1 Gbps, 12 12 Digital Crosspoint Switch data sheet adn4612 . FEATURES FUNCTIONAL BLOCK DIAGRAM. DVCC VCC. DC to Gbps per port, NRZ data rate Multitime constant, programmable receive equalization Compensates 25 inches of FR408 at Gbps IP11 OP11. Compensates 15 inches of FR408 at Gbps TO IP0 Rx Tx TO OP0. 12 12. 6-tap programmable transmit feedforward equalization (FFE) VTTIE, VTTIW Switch . PRE- EMPHASIS. VTTON, VTTOS. Compensates 15 inches of FR408 at Gbps IN11 EQ. MATRIX. ON11. Compensates 10 inches of FR408 at Gbps TO IN0 TO ON0. Low power 150 mW per channel at V (outputs enabled) Rx CONTROL.

2 XPT CONTROL. Tx CONTROL. CONNECTIVITY. 12 12, fully differential, nonblocking array EQUALIZATION. MAP (A/B/C/D). 6-TAP FFE. SIGNAL DETECT OUTPUT LEVEL. Double rank connection programming SELECT. 2-pin selectable connection maps Per lane lost of signal (LOS) detection EEPROM. Flexible output termination supply range ( V to V) MAP1, MAP0. DC- or ac-coupled differential CML inputs and outputs RESET. Programmable CML output levels UPDATE SERIAL. INTERFACE. Load from EEPROM for automatic power-on ready operation SPI/I2C CONTROL. LOGIC. Per lane input and output P/N pair inversion for routing ease SCK/SCL.

3 SDO/SDA. 50 on-chip input/output termination adn4612 . SDI/I2C_A1. Supports 64-bit/66-bit, scrambled or not coded NRZ data up CS/I2C_A0. to Gbps LOS_IRQ. 11020-001. Serial (I2C or SPI slave) control interface VEE. 88-lead LFCSP, 12 mm 12 mm, Pb-free package Figure 1. 40 C to +85 C operating temperature range APPLICATIONS. Fiber optic network switching 10 Gigabit Ethernet over backplane 10 GBASE-KR XLAUI/CAUI ( ). SONET OC-192/STM-64x 1 , 2 , 4 , 8 , and 10 Fibre Channel GENERAL DESCRIPTION. The adn4612 is a 12 12 asynchronous, protocol agnostic, Digital The adn4612 nonblocking Switch core implements a 12 12.

4 Crosspoint Switch with 12 differential PECL-/CML-compatible crossbar and supports independent channel switching through inputs and 12 differential CML outputs. the serial control interface. The adn4612 has low latency and The adn4612 is optimized for nonreturn-to-zero (NRZ) signaling very low channel-to-channel skew. with data rates of up to Gbps per port. Each port provides The adn4612 is packaged in an 88-lead LFCSP package and programmable input equalization, loss of signal (LOS) detection, operates from 40 C to +85 C. programmable output swing, and output preemphasis/deemphasis.

5 Rev. C Document Feedback Information furnished by analog devices is believed to be accurate and reliable. However, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, Box 9106, Norwood, MA 02062-9106, license is granted by implication or otherwise under any patent or patent rights of analog devices . Tel: 2013 2016 analog devices , Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners.

6 Technical Support adn4612 data sheet TABLE OF CONTENTS. Features .. 1 Register Descriptions .. 47. Applications .. 1 Software Reset Register .. 47. Functional Block Diagram .. 1 Tx Enable Control Registers .. 47. General Description .. 1 Tx Reference Enable Register .. 48. Revision History .. 3 Squelch Control Register .. 48. 4 Rx and Tx Swap Sign 48. Input/Output 4 XPT Broadcast Lane Number Register .. 50. Power Supply and Thermal Specifications .. 5 Tx 0 Driver Control Registers .. 50. Electrical Specifications Control Logic Pins .. 6 Tx 0 Driver Enable Registers.

7 52. I C Master and Slave Timing Specifications .. 6. 2. Tx 0 Driver Resolution Registers .. 53. SPI Timing Specifications .. 7 Tx 1 Driver Control Registers .. 53. EEPROM Master I C Timing Specifications .. 8. 2. Tx 1 Driver Enable Registers .. 53. RESET Timing Specifications .. 9 Tx 1 Driver Resolution Registers .. 53. Absolute Maximum 10 Tx 2 Driver Control Registers .. 54. Thermal Resistance .. 10 Tx 2 Driver Enable Registers .. 54. ESD Caution .. 10 Tx 2 Driver Resolution Registers .. 54. Pin Configuration and Function Descriptions .. 11 Tx 3 Driver Control Registers.

8 54. Typical Performance Characteristics .. 13 Tx 3 Driver Enable Registers .. 54. Standard Test .. 17 Tx 3 Driver Resolution Registers .. 54. Equalization Test .. 18 Tx 4 Driver Control Registers .. 54. Preemphasis Test .. 20 Tx 4 Driver Enable Registers .. 54. Test Circuits .. 22 Tx 4 Driver Resolution Registers .. 55. Theory of Operation .. 23 Tx 5 Driver Control Registers .. 55. Introduction .. 23 Tx 5 Driver Enable Registers .. 55. Receivers .. 24 Tx 5 Driver Resolution Registers .. 55. Switch Core .. 26 Tx 6 Driver Control Registers .. 55. Transmitters.

9 27 Tx 6 Driver Enable Registers .. 55. Preemphasis/Deemphasis Support for Legacy Rates .. 33 Tx 6 Driver Resolution Registers .. 55. Load from Memory .. 34 Tx 7 Driver Control Registers .. 55. I2C Serial Control Interface .. 37 Tx 7 Driver Enable Registers .. 55. I2C data Write .. 37 Tx 7 Driver Resolution Registers .. 56. I2C data Read .. 38 Tx 8 Driver Control Registers .. 56. SPI Serial Control 39 Tx 8 Driver Enable Registers .. 56. Write Operation .. 39 Tx 8 Driver Resolution Registers .. 56. Read Operation .. 39 Tx 9 Driver Control Registers.

10 56. Applications Information .. 40 Tx 9 Driver Enable Registers .. 56. Applications Circuit .. 41 Tx 9 Driver Resolution Registers .. 56. Power Consumption .. 41 Tx 10 Driver Control Registers .. 56. Printed Circuit Board (PCB) Layout Guidelines .. 42 Tx 10 Driver Enable Registers .. 56. Register 44 Tx 10 Driver Resolution Registers .. 57. Rev. C | Page 2 of 76. data sheet adn4612 . Tx 11 Driver Control Registers ..57 Rx 11 to Rx 6 LOS Assert and Deassert Level Control Tx 11 Driver Enable Registers ..57 Register .. 66 Tx 11 Driver Resolution Registers.