Lecture 9: Circuit Families - cmosvlsi.com

1 Introduction to cmos vlsi . Design Lecture 9: Circuit Families David Harris Harvey Mudd College Spring 2004. Outline q Pseudo-nMOS Logic q Dynamic Logic q Pass Transistor Logic 9: Circuit Families cmos vlsi Design Slide 2. Introduction q What makes a Circuit fast? I = C dV/dt -> tpd (C/I) V. low capacitance high current small swing B 4. A 4. q Logical effort is proportional to C/I Y. 1 1. q pMOS are the enemy! High capacitance for a given current q Can we take the pMOS capacitance off the input? q Various Circuit Families try to do this . 9: Circuit Families cmos vlsi Design Slide 3. Pseudo-nMOS. q In the old days, nMOS processes had no pMOS. Instead, use pull-up transistor that is always ON.

2 Q In cmos , use a pMOS that is always ON. Ratio issue Make pMOS about effective strength of pulldown network load P/2 P = 24. Ids Vout Vout P = 14. 16/2 P=4. Vin 0. 0 Vin 9: Circuit Families cmos vlsi Design Slide 4. Pseudo-nMOS Gates q Design for unit current on output to compare with unit inverter. Y. q pMOS fights nMOS inputs f Inverter NAND2 NOR2. gu = gu = gu =. gd = g = gd =. gavg = Y gd = gavg =. avg A. Y pu = pu = Y pu =. A pd = B pd = A B pd =. pavg = pavg = pavg =. 9: Circuit Families cmos vlsi Design Slide 5. Pseudo-nMOS Gates q Design for unit current on output to compare with unit inverter. Y. q pMOS fights nMOS inputs f Inverter NAND2 NOR2. gu = gu = gu =.

3 Gd = 2/3 g = gd =. gavg = Y gd = gavg =. 2/3 avg 2/3. A 8/3. Y pu = pu = Y pu =. A 4/3 pd = B 8/3 pd = A 4/3 B 4/3 pd =. pavg = pavg = pavg =. 9: Circuit Families cmos vlsi Design Slide 6. Pseudo-nMOS Gates q Design for unit current on output to compare with unit inverter. Y. q pMOS fights nMOS inputs f Inverter NAND2 NOR2. gu = 4/3 gu = 8/3 gu = 4/3. gd = 4/9 2/3 g = 8/9 gd = 4/9. gavg = 8/9 Y gd = 16/9 gavg = 8/9. 2/3 avg 2/3. A 8/3. Y pu = pu = Y pu =. A 4/3 pd = B 8/3 pd = A 4/3 B 4/3 pd =. pavg = pavg = pavg =. 9: Circuit Families cmos vlsi Design Slide 7. Pseudo-nMOS Gates q Design for unit current on output to compare with unit inverter. Y. q pMOS fights nMOS inputs f Inverter NAND2 NOR2.

4 Gu = 4/3 gu = 8/3 gu = 4/3. gd = 4/9 2/3 g = 8/9 gd = 4/9. gavg = 8/9 Y gd = 16/9 gavg = 8/9. 2/3 avg 2/3. A 8/3. Y pu = 6/3 pu = 10/3 Y pu = 10/3. A 4/3 pd = 6/9 B 8/3 pd = 10/9 A 4/3 B 4/3 pd = 10/9. pavg = 12/9 pavg = 20/9 pavg = 20/9. 9: Circuit Families cmos vlsi Design Slide 8. Pseudo-nMOS Design q Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H. Pseudo-nMOS. q G= In1 1. Y. q F= H. Ink 1. q P=. q N=. q D=. 9: Circuit Families cmos vlsi Design Slide 9. Pseudo-nMOS Design q Ex: Design a k-input AND gate using pseudo-nMOS. Estimate the delay driving a fanout of H. Pseudo-nMOS. q G = 1 * 8/9 = 8/9 In1 1. Y. q F = GBH = 8H/9 H.

5 Ink 1. q P = 1 + (4+8k)/9 = (8k+13)/9. q N=2. 4 2 H 8k + 13. q D = NF + P = 3 + 9. 1/N. 9: Circuit Families cmos vlsi Design Slide 10. Pseudo-nMOS Power q Pseudo-nMOS draws power whenever Y = 0. Called static power P = I VDD. A few mA / gate * 1M gates would be a problem This is why nMOS went extinct! q Use pseudo-nMOS sparingly for wide NORs q Turn off pMOS when not in use en Y. A B C. 9: Circuit Families cmos vlsi Design Slide 11. Dynamic Logic q Dynamic gates uses a clocked pMOS pullup q Two modes: precharge and evaluate 2 2/3 1. A Y Y Y. 1 A 4/3 A 1. Static Pseudo-nMOS Dynamic Precharge Evaluate Precharge Y. 9: Circuit Families cmos vlsi Design Slide 12. The Foot q What if pulldown network is ON during precharge?

6 Q Use series evaluation transistor to prevent fight.. precharge transistor Y Y. Y inputs inputs A f f foot footed unfooted 9: Circuit Families cmos vlsi Design Slide 13. Logical Effort Inverter NAND2 NOR2. 1. Y. 1 1. A 2. unfooted Y Y. A 1 B 2 A 1 B 1. gd = gd = gd =. pd = pd = pd =. 1. Y. 1 1. A 3. Y Y. footed A 2 B 3 A 2 B 2. gd = gd = gd =. 2 pd = 3 pd = 2 pd =. 9: Circuit Families cmos vlsi Design Slide 14. Logical Effort Inverter NAND2 NOR2. 1. Y. 1 1. A 2. unfooted Y Y. A 1 B 2 A 1 B 1. gd = 1/3 gd = 2/3 gd = 1/3. pd = 2/3 pd = 3/3 pd = 3/3. 1. Y. 1 1. A 3. Y Y. footed A 2 B 3 A 2 B 2. gd = 2/3 gd = 3/3 gd = 2/3. 2 pd = 3/3 3 pd = 4/3 2 pd = 5/3. 9: Circuit Families cmos vlsi Design Slide 15.

7 Monotonicity q Dynamic gates require monotonically rising inputs during evaluation . 0 -> 0. A. 0 -> 1. 1 -> 1. violates monotonicity But not 1 -> 0 during evaluation A. Precharge Evaluate Precharge Y. Output should rise but does not 9: Circuit Families cmos vlsi Design Slide 16. Monotonicity Woes q But dynamic gates produce monotonically falling outputs during evaluation q Illegal for one dynamic gate to drive another! A=1. Precharge Evaluate Precharge Y. X. A. X. Y. 9: Circuit Families cmos vlsi Design Slide 17. Monotonicity Woes q But dynamic gates produce monotonically falling outputs during evaluation q Illegal for one dynamic gate to drive another! A=1. Precharge Evaluate Precharge Y.

8 X. A. X. X monotonically falls during evaluation Y. Y should rise but cannot 9: Circuit Families cmos vlsi Design Slide 18. Domino Gates q Follow dynamic stage with inverting static gate Dynamic / static pair is called domino gate Produces monotonic outputs Precharge Evaluate Precharge domino AND. W. W X Y Z X. A. Y. B C.. Z. dynamic static . NAND inverter . A W X A X. H Y =. B H Z B Z. C C. 9: Circuit Families cmos vlsi Design Slide 19. Domino Optimizations q Each domino gate triggers next one, like a string of dominos toppling over q Gates evaluate sequentially but precharge in parallel q Thus evaluation is more critical than precharge q HI-skewed static stages can perform logic.

9 S0 S1 S2 S3. D0 D1 D2 D3. Y. H.. S4 S5 S6 S7. D4 D5 D6 D7. 9: Circuit Families cmos vlsi Design Slide 20. Dual-Rail Domino q Domino only performs noninverting functions: AND, OR but not NAND, NOR, or XOR. q Dual-rail domino solves this problem Takes true and complementary inputs Produces true and complementary outputs sig_h sig_l Meaning 0 0 Precharged Y_l Y_h inputs 0 1 0' f f 1 0 1' . 1 1 invalid 9: Circuit Families cmos vlsi Design Slide 21. Example: AND/NAND. q Given A_h, A_l, B_h, B_l q Compute Y_h = A * B, Y_l = ~(A * B). 9: Circuit Families cmos vlsi Design Slide 22. Example: AND/NAND. q Given A_h, A_l, B_h, B_l q Compute Y_h = A * B, Y_l = ~(A * B). q Pulldown networks are conduction complements Y_l Y_h = A*B A_h = A*B.

10 A_l B_l B_h . 9: Circuit Families cmos vlsi Design Slide 23. Example: XOR/XNOR. q Sometimes possible to share transistors Y_l Y_h = A xnor B A_h A_l A_l A_h = A xor B. B_l B_h . 9: Circuit Families cmos vlsi Design Slide 24. Leakage q Dynamic node floats high during evaluation Transistors are leaky (IOFF 0). Dynamic value will leak away over time Formerly miliseconds, now nanoseconds! q Use keeper to hold dynamic node Must be weak enough not to fight evaluation weak keeper 1 k X. H Y. A 2. 2. 9: Circuit Families cmos vlsi Design Slide 25. Charge Sharing q Dynamic gates suffer from charge sharing .. Y A. A x CY. Y. B=0 Cx x 9: Circuit Families cmos vlsi Design Slide 26.