1 V, 100 Mbps, Half- and Full-Duplex, High Speed M-LVDS Transceivers Data Sheet ADN4690E/ADN4692E/ADN4694E/ADN4695E Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, Box 9106, Norwood, MA 02062-9106, Tel: 2012 2016 Analog Devices, Inc.
2 All rights reserved. Technical Support FEATURES Multipoint LVDS transceivers (low voltage differential signaling driver and receiver pairs) Switching rate: 100 Mbps (50 MHz) Supported bus loads: 30 to 55 Choice of 2 receiver types Type 1 (ADN4690E/ADN4692E): hysteresis of 25 mV Type 2 (ADN4694E/ADN4695E): threshold offset of 100 mV for open-circuit and bus-idle fail-safe Conforms to TIA/EIA-899 standard for M-LV D S Glitch-free power-up/power-down on M-LVDS bus Controlled transition times on driver output Common-mode range: 1 V to + V, allowing communication with 2 V of ground noise Driver outputs high-Z when disabled or powered off Enhanced ESD protection on bus pins 15 kV HBM (human body model), air discharge 8 kV HBM (human body model), contact discharge 10 kV IEC 61000-4-2, air discharge 8 kV IEC 61000-4-2, contact discharge Operating temperature range.
3 40 C to +85 C Available in 8-lead (ADN4690E/ADN4694E) and 14-lead (ADN4692E/ADN4695E) SOIC packages APPLICATIONS Backplane and cable multipoint data transmission Multipoint clock distribution Low power, high Speed alternative to shorter RS-485 links Networking and wireless base station infrastructure FUNCTIONAL BLOCK DIAGRAMS ADN4690E/ADN4694 EVCCGNDRORDREDEABDI10471-001 Figure 1. ADN4692E/ADN4695 EVCCGNDRORDREDEDI10471-102 ABZY Figure 2. GENERAL DESCRIPTION The ADN4690E/ADN4692E/ADN4694E/ADN4695E are multipoint, low voltage differential signaling (M-LV D S ) transceivers (driver and receiver pairs) that can operate at up to 100 Mbps (50 MHz). Slew rate control is implemented on the driver outputs. The receivers detect the bus state with a differential input of as little as 50 mV over a common-mode voltage range of 1 V to + V.
4 ESD protection of up to 15 kV is implemented on the bus pins. The parts adhere to the TIA/EIA-899 standard for M-LVDS and complement TIA/EIA-644 LVDS devices with additional multipoint capabilities. The ADN4690E/ADN4692E are Type 1 receivers with 25 mV of hysteresis, so that slow-changing signals or loss of input does not lead to output oscillations. The ADN4694E/ADN4695E are Type 2 receivers exhibiting an offset threshold, guaranteeing the output state when the bus is idle (bus-idle fail-safe) or the inputs are open (open-circuit fail-safe). The parts are available as Half- duplex in an 8-lead SOIC package (the ADN4690E/ADN4694E) or as full-duplex in a 14-lead SOIC package (the ADN4692E/ADN4695E). A selection table for the ADN469xE parts is shown in Ta b l e 1.
5 Table 1. High Speed M-LVDS Transceiver Selection Table Part No. Receiver Data Rate SOIC Duplex ADN4690E Type 1 100 Mbps 8-lead Half ADN4691E Type 1 200 Mbps 8-lead Half ADN4692E Type 1 100 Mbps 14-lead Full ADN4693E Type 1 200 Mbps 14-lead Full ADN4694E Type 2 100 Mbps 8-lead Half ADN4695E Type 2 100 Mbps 14-lead Full ADN4696E Type 2 200 Mbps 8-lead Half ADN4697E Type 2 200 Mbps 14-lead Full ADN4690E/ADN4692E/ADN4694E/ADN4695E Data Sheet Rev. B | Page 2 of 20 TABLE OF CONTENTS Features .. 1 Applications .. 1 Functional Block Diagrams .. 1 General Description .. 1 Revision History .. 2 Specifications .. 3 Receiver Input Threshold Test Voltages .. 4 Timing Specifications .. 5 Absolute Maximum Ratings .. 6 Thermal Resistance.
6 6 ESD Caution .. 6 Pin Configurations and Function Descriptions .. 7 Typical Performance Characteristics .. 8 Te s t Circuits and Switching Characteristics .. 11 Driver Voltage and Current Measurements .. 11 Driver Timing Measurements .. 12 Receiver Timing Measurements .. 13 Theory of Operation .. 14 Half- Duplex/Full-Duplex Operation .. 14 Three-State Bus Connection .. 14 Tr u t h Ta b l e 14 Glitch-Free Power-Up/Power-Down .. 15 Fault Conditions .. 15 Receiver Input Thresholds/Fail-Safe .. 15 Applications Information .. 16 Outline Dimensions .. 17 Ordering Guide .. 17 REVISION HISTORY 1/16 Rev. A to Rev. B Changed NC to DNC .. Throughout Changes to Table 1 Title .. 1 Changes to Table 6 .. 6 3/12 Rev. 0 to Rev.
7 A Added ADN4694E and ADN4695E .. Universal Change to Features Section, General Description Section, and Table 1 .. 1 Added Type 2 Receiver Parameters, Table 2 .. 3 Added Table 4, Renumbered Sequentially .. 5 Added Type 2 Receiver Parameters, Table 5 .. 5 Changes to Table 8 .. 7 Added Table 13 .. 14 Changes to Receiver Input Thresholds/Fail-Safe Section and Figure 35 .. 15 Changes to Figure 36 and Figure 37 and Their Captions .. 16 Changes to Ordering Guide .. 18 1/12 Revision 0: Initial Version Data Sheet ADN4690E/ADN4692E/ADN4694E/ADN4695E Rev. B | Page 3 of 20 SPECIFICATIONS VCC = V to V; RL = 50 ; TA = TMIN to TMAX, unless otherwise Table 2. Parameter Symbol Min Typ Max Unit Test Conditions/Comments DRIVER Differential Outputs Differential Output Voltage Magnitude |VOD| 480 650 mV See Figure 18 |VOD| for Complementary Output States |VOD| 50 +50 mV See Figure 18 Common-Mode Output Voltage (Steady State) VOC(SS) V See Figure 19, Figure 22 VOC(SS) for Complementary Output States VOC(SS) 50 +50 mV See Figure 19, Figure 22 Peak-to-Peak VOC VOC(PP) 150 mV See Figure 19, Figure 22 Maximum Steady-State Open-Circuit Output Voltage VA(O), VB(O), VY(O), or VZ(O)
8 0 V See Figure 20 Voltage Overshoot Low to High VPH V See Figure 23, Figure 26 High to Low VPL V See Figure 23, Figure 26 Output Current Short Circuit |IOS| 24 mA See Figure 21 High Impedance State, Driver Only IOZ 15 +10 A V (VY or VZ) V, other output = V Power Off IO(OFF) 10 +10 A V (VY or VZ) V, other output = V, 0 V VCC V Output Capacitance CY or CZ 3 pF VI = sin(30e6 t) V + V,2 other output = V, DE = 0 V Differential Output Capacitance CYZ pF VAB = sin(30e6 t) V,2 DE = 0 V Output Capacitance Balance (CY/CZ) CY/Z Logic Inputs (DI, DE) Input High Voltage VIH 2 VCC V Input Low Voltage VIL GND V Input High Current IIH 0 10 A VIH = 2 V to VCC Input Low Current IIL 0 10 A VIL = GND to V RECEIVER Differential Inputs Differential Input Threshold Voltage Type 1 Receiver (ADN4690E, ADN4692E) VTH 50 +50 mV See Table 3, Figure 35 Type 2 Receiver (ADN4694E, ADN4695E) VTH 50 150 mV See Table 4, Figure 35 Input Hysteresis Type 1 Receiver (ADN4690E, ADN4692E) VHYS 25 mV Type 2 Receiver (ADN4694E, ADN4695E) VHYS 0 mV Differential Input Voltage Magnitude |VID| VCC V Input Capacitance CA or CB 3 pF VI = sin(30e6 t) V + V,2 other input = V Differential Input Capacitance CAB pF VAB = sin(30e6 t)
9 V2 Input Capacitance Balance (CA/CB) CA/B Logic Output RO Output High Voltage VOH V IOH = 8 mA Output Low Voltage VOL V IOL = 8 mA High Impedance Output Current IOZ 10 +15 A VO = 0 V or V Logic Input RE Input High Voltage VIH 2 VCC V Input Low Voltage VIL GND V Input High Current IIH 10 0 A VIH = 2 V to VCC Input Low Current IIL 10 0 A VIL = GND to V ADN4690E/ADN4692E/ADN4694E/ADN4695E Data Sheet Rev. B | Page 4 of 20 Parameter Symbol Min Typ Max Unit Test Conditions/Comments
10 BUS INPUT/OUTPUT Input Current A (Receiver or Transceiver with Driver Disabled) IA 0 32 A VB = V, VA = V 20 +20 A VB = V.