a 8-Bit, 100 MSPS+ D/A Converter AD9708 - Analog Devices

1 REV. BInformation furnished by Analog Devices is believed to be accurate andreliable. However, no responsibility is assumed by Analog Devices for itsuse, nor for any infringements of patents or other rights of third partieswhich may result from its use. No license is granted by implication orotherwise under any patent or patent rights of Analog Technology Way, Box 9106, Norwood, MA 02062-9106, : 781/329-4700 World Wide Web Site: : 781/326-8703 Analog Devices , Inc., 19998-Bit, 100 MSPS+ TxDAC D/A ConverterFUNCTIONAL BLOCK DIAGRAM+ REFREFLOREF IOFS +5 VAVDDSEGMENTEDSWITCHESLATCHESDIGITAL DATA INPUTS (DB7 DB0) + of Pin-Compatible TxDAC Product Family125 MSPS Update Rate8-Bit ResolutionLinearity: 1/4 LSB DNLL inearity: 1/4 LSB INLD ifferential Current OutputsSINAD @ 5 MHz Output: 50 dBPower Dissipation: 175 mW @ 5 V to 45 mW @ 3 VPower-Down Mode: 20 mW @ 5 VOn-Chip V ReferenceSingle +5 V or +3 V Supply OperationPackages: 28-Lead SOIC and 28-Lead TSSOPEdge-Triggered LatchesFast Settling: 35 ns Full-Scale Settling to ReconstructionInstrumentationPRODUCT DESCRIPTIONThe AD9708 is the 8-bit resolution member of the TxDACseries of high performance, low power CMOS digital-to-analogconverters (DACs).

2 The TxDAC family, which consists of pincompatible 8-, 10-, 12-, and 14-bit DACs, was specifically opti-mized for the transmit signal path of communication systems. Allof the Devices share the same interface options, small outlinepackage and pinout, thus providing an upward or downwardcomponent selection path based on performance, resolution andcost. The AD9708 offers exceptional ac and dc performancewhile supporting update rates up to 125 AD9708 s flexible single-supply operating range of + Vto + V and low power dissipation are well suited for portableand low power applications. Its power dissipation can befurther reduced to 45 mW, without a significant degradation inperformance, by lowering the full-scale current output. In addi-tion, a power-down mode reduces the standby power dissipa-tion to approximately 20 AD9708 is manufactured on an advanced CMOS segmented current source architecture is combined with aproprietary switching technique to reduce spurious componentsand enhance dynamic performance.

3 Edge-triggered input latchesand a temperature compensated bandgap reference have been inte-grated to provide a complete monolithic DAC solution. Flexiblesupply options support +3 V and +5 V CMOS logic AD9708 is a current-output DAC with a nominal full-scaleoutput current of 20 mA and > 100 k output is a registered trademark of Analog Devices , current outputs are provided to support single-ended or differential applications. The current outputs may bedirectly tied to an output resistor to provide two complemen-tary, single-ended voltage outputs. The output voltage compliancerange is AD9708 contains a V on-chip reference and referencecontrol amplifier, which allows the full-scale output current tobe simply set by a single resistor. The AD9708 can be driven bya variety of external reference voltages. The AD9708 s full-scalecurrent can be adjusted over a 2 mA to 20 mA range withoutany degradation in dynamic performance.

4 Thus, the AD9708may operate at reduced power levels or be adjusted over a 20 dBrange to provide additional gain ranging AD9708 is available in 28-lead SOIC and 28-lead TSSOP packages. It is specified for operation over the industrial tem-perature HIGHLIGHTS1. The AD9708 is a member of the TxDAC product family, whichprovides an upward or downward component selection pathbased on resolution (8 to 14 bits), performance and Manufactured on a CMOS process, the AD9708 uses a pro-prietary switching technique that enhances dynamic perfor-mance well beyond 8- and 10-bit video On-chip, edge-triggered input CMOS latches readily interfaceto +3 V and +5 V CMOS logic families. The AD9708 cansupport update rates up to 125 A flexible single-supply operating range of + V to + Vand a wide full-scale current adjustment span of 2 mA to20 mA allows the AD9708 to operate at reduced power levels( , 45 mW) without any degradation in dynamic A temperature compensated, V bandgap reference isincluded on-chip providing a complete DAC solution.

5 Anexternal reference may be The current output(s) of the AD9708 can easily be config-ured for various single-ended or differential SPECIFICATIONSP arameterMinTypMaxUnitsRESOLUTION8 BitsMONOTONICITYGUARANTEED OVER SPECIFIED TEMPERATURE RANGEDC ACCURACY1 Integral Linearity Error (INL) 1/2 1/4+1/2 LSBD ifferential Nonlinearity (DNL) 1/2 1/4+1/2 LSBANALOG OUTPUTO ffset Error + of FSRGain Error (Without Internal Reference) 10 2+10% of FSRGain Error (With Internal Reference) 10 1+10% of FSRFull-Scale Output Compliance Range Resistance100k Output Capacitance5pFREFERENCE OUTPUTR eference Output Current3100nAREFERENCE INPUTI nput Compliance Input Resistance1M Small Signal Bandwidth (w/o CCOMP1) COEFFICIENTSO ffset Drift0ppm of FSR/ CGain Drift (Without Internal Reference) 50ppm of FSR/ CGain Drift (With Internal Reference) 100ppm of FSR/ CReference Voltage Drift 50ppm/ CPOWER SUPPLYS upply Supply Current (IAVDD)2530mADigital Supply Current (IDVDD)636mASupply Current Sleep Mode (IAVDD) Dissipation6 (5 V, IOUTFS = 20 mA)140175mWPower Dissipation7 (5 V, IOUTFS = 20 mA)190mWPower Dissipation7 (3 V, IOUTFS = 2 mA)

6 45mWPower Supply Rejection Ratio AVDD + of FSR/VPower Supply Rejection Ratio DVDD + of FSR/VOPERATING RANGE 40+85 CNOTES1 Measured at IOUTA, driving a virtual full-scale current, IOUTFS, is 32 the IREF an external buffer amplifier to drive any external bandwidth is a function of external cap at COMP1 operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum at fCLOCK = 50 MSPS and fOUT = as unbuffered voltage output into 50 RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 subject to change without notice.(TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted) 2 REV. BAD9708 SPECIFICATIONSDYNAMIC SPECIFICATIONSP arameterMinTypMaxUnitsDYNAMIC PERFORMANCEM aximum Output Update Rate (fCLOCK)100125 MSPSO utput Settling Time (tST) (to )135nsOutput Propagation Delay (tPD)1nsGlitch Impulse5pV-sOutput Rise Time (10% to 90%) Fall Time (10% to 90%) Noise (IOUTFS = 20 mA)50pA/ HzOutput Noise (IOUTFS = 2 mA)30pA/ HzAC LINEARITY TO NYQUISTS ignal-to-Noise and Distortion RatiofCLOCK = 10 MSPS; fOUT = MHz50dBfCLOCK = 50 MSPS; fOUT = MHz50dBfCLOCK = 50 MSPS; fOUT = MHz48dBfCLOCK = 100 MSPS; fOUT = MHz50dBfCLOCK = 100 MSPS; fOUT = MHz45dBTotal Harmonic DistortionfCLOCK = 10 MSPS; fOUT = MHz 67dBcfCLOCK = 50 MSPS; fOUT = MHz 67 62dBcfCLOCK = 50 MSPS; fOUT = MHz 59dBcfCLOCK = 100 MSPS; fOUT = MHz 64dBcfCLOCK = 100 MSPS; fOUT = MHz 48dBcSpurious-Free Dynamic Range to NyquistfCLOCK = 10 MSPS.

7 FOUT = MHz68dBcfCLOCK = 50 MSPS; fOUT = MHz6268dBcfCLOCK = 50 MSPS; fOUT = MHz63dBcfCLOCK = 100 MSPS; fOUT = MHz67dBcfCLOCK = 100 MSPS; fOUT = MHz50dBcNOTES1 Measured single ended into 50 subject to change without SPECIFICATIONSP arameterMinTypMaxUnitsDIGITAL INPUTSL ogic 1 Voltage @ DVDD = +5 1 Voltage @ DVDD = +3 0 Voltage @ DVDD = +5 0 Voltage @ DVDD = +3 1 Current 10+10 ALogic 0 Current 10+10 AInput Capacitance5pFInput Setup Time (tS) Hold Time (tH) Pulsewidth (tLPW) subject to change without tS tH tLPW tPD tSTDB0 DB7 CLOCKIOUTAORIOUTBF igure 1. Timing Diagram(TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, Single-Ended Output, IOUTA, 50V DoublyTerminated, unless otherwise noted) AD9708 3 REV. B(TMIN to TMAX, AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA unless otherwise noted) AD9708 4 REV. BABSOLUTE MAXIMUM RATINGS*WithParameterRespect toMinMaxUnitsAVDDACOM + + + + , SLEEPDCOM + InputsDCOM + , IOUTBACOM + , COMP2 ACOM + , FSADJACOM + + Temperature+150 CStorage Temperature 65+150 CLead Temperature(10 sec)+300 C*Stresses above those listed under Absolute Maximum Ratings may cause perma-nent damage to the device.

8 This is a stress rating only; functional operation of thedevice at these or any other conditions above those indicated in the operationalsections of this specification is not implied. Exposure to absolute maximumratings for extended periods may effect device CHARACTERISTICST hermal Resistance28-Lead 300 mil SOIC JA = C/W JC = 23 C/W28-Lead TSSOP JA = C/W JC = C/WPIN CONFIGURATION141312111716152019181098123 4765 TOP VIEW(Not to Scale)2827262524232221AD9708NC = NO CONNECT(MSB) DB7DB6DB5DB4DB3DB2DB1DB0 NCNCNCNCNCNCCLOCKDVDDDCOMNCAVDDCOMP2 IOUTAIOUTBACOMCOMP1FS ADJREFIOREFLOSLEEPCAUTIONESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readilyaccumulate on the human body and test equipment and can discharge without the AD9708 features proprietary ESD protection circuitry, permanent damage mayoccur on Devices subjected to high energy electrostatic discharges.

9 Therefore, proper ESDprecautions are recommended to avoid performance degradation or loss of FUNCTION DESCRIPTIONSPin No. NameDescription1DB7 Most Significant Data Bit (MSB).2 7DB6 DB1 Data Bits 1 Significant Data Bit (LSB).9 14, 25 NCNo Internal Control Input. ActiveHigh. Contains active pull-down circuit,thus may be left unterminated if Ground when Internal VReference Used. Connect to AVDD todisable internal Input/Output. Serves asreference input when internal referencedisabled ( , Tie REFLO to AVDD).Serves as V reference output wheninternal reference activated ( , TieREFLO to ACOM). Requires Fcapacitor to ACOM when internalreference ADJFull-Scale Current Output Reduction F to AVDD for DAC Current current when all data bitsare Current Output. Full-scalecurrent when all data bits are Bias Node for Switch DriverCircuitry.

10 Decouple to ACOM F Supply Voltage (+ V to+ V).26 DCOMD igital Supply Voltage (+ V to+ V).28 CLOCKC lock Input. Data latched on positiveedge of GUIDET emperaturePackagePackageModelRangeDescri ptionsOptions*AD9708AR 40 C to +85 C 28-Lead 300 Mil SOICR-28AD9708 ARU 40 C to +85 C 28-Lead TSSOPRU-28AD9708-EBEvaluation Board*R = Small Outline IC; RU = Thin Small Outline !ESD SENSITIVE DEVICEAD9708 5 REV. BDEFINITIONS OF SPECIFICATIONSL inearity Error (Also Called Integral Nonlinearity or INL)Linearity error is defined as the maximum deviation of theactual Analog output from the ideal output, determined by astraight line drawn from zero to full Nonlinearity (or DNL)DNL is the measure of the variation in Analog value, normalizedto full scale, associated with a 1 LSB change in digital input D/A Converter is monotonic if the output either increases orremains constant as the digital input ErrorThe deviation of the output current from the ideal of zero iscalled offset error.