A Technical Tutorial on Digital Signal Synthesis

1 Copyright 1999 Analog Devices, Technical Tutorialon Digital Signal Synthesis Copyright 1999 Analog Devices, 1. Fundamentals of DDS technologyTheory of operationCircuit architectureTuning equationElements of DDS circuit functionality and capabilitiesDAC integrationTrends in functional integrationSection 2. Understanding the Sampled Output of a DDS OutputImplications of the Nyquist TheorumAliased images in the outputSource of aliased imagesCalculating the occurrence of aliased imagesQuantization considerationsSin(X)/X responseAC and DC linearity of the outputSection 3. Frequency/phase-hopping Capability of DDSC alculating the output tuning wordDetermining maximum tuning resolutionDetermining maximum tuning speedUnderstanding the DDS control interfacePre-programming profile registersSection 4.

2 The DDS Output SpectrumThe effect of DAC resolution on spurious performanceThe effect of oversampling on spurious performanceThe effect of truncating the phase accumulator on spurious performanceAdditional DDS Spur sourcesWideband spur performanceNarrowband spur performancePredicting and exploiting spur "sweet spots" in a DDS' tuning rangeJitter and phase noise considerations in a DDS systemOutput filtering considerationsSection 5. High-speed Reference Clock ConsiderationsImplications of jitter and phase noise in the reference clockReference clock multipliersSFDR performance vs. the REFCLK Multiplier functionCopyright 1999 Analog Devices, 6.

3 Interfacing to the DDS OutputOutput power considerationsFS output current range and tradeoffs vs. spur performanceSingle-ended vs. differential DAC outputDriving an output amplifierSection 7. DDS as a Clock GeneratorDefinition of clock generator application for a DDSS quaring the DDS output with an LP filter and comparatorManaging jitter in the clock generator applicationSection 8. Replacing/Integrating a PLL with a DDS SolutionTraditional analog synthesizer vs. the DDS implementationHow DDS can eliminate analog upconverter stagesExample of implementation of DDS as an LOSection 9. Digital Modulator Application of DDSB asic Digital modulator theorySystem architecture and requirementsDigital filtersMultirate DSPC lock and input data synchronization considerationsData encoding methodologies and DDS implementationsSection 10.

4 Using Aliased Images to Generate Nyquist + Frequencies from a DDSC reating and isolating aliased images in the DDS output spectrumSFDR performance expectations of the aliased imageAmplitude prediction of the aliased imageFrequency hopping considerations in the aliased image applicationSection 11. Ancillary DDS Techniques, Features, and FunctionsImproving SFDR with the addition of phase dither in the phase accumulatorUnderstanding DDS frequency chirp functionalityAchieving output amplitude control/modulation within a DDS deviceSynchronization multiple DDS devicesSection 12. Techniques for Bench Evaluation of a DDS SolutionPC-based evaluation platforms and reference designsCopyright 1999 Analog Devices, 13.

5 Integrating DDS-based Hardware into a System EnvironmentAnalog/ Digital ground considerationsPower supply considerationsHigh-speed PCB layout techniquesSection 14. DDS Product Selection GuideAppendix A Glossary of Related Electronic TermsAppendix B Common Communications AcronymsAppendix C An FM Modulator using DDSA ppendix D Pseudo-Random GeneratorAppendix E - Jitter Reduction in DDS Clock Generator SystemsCopyright 1999 Analog Devices, 1. Fundamentals of DDS TechnologyOverviewDirect Digital Synthesis (DDS) is a technique for using Digital data processing blocks as a meansto generate a frequency- and phase-tunable output Signal referenced to a fixed-frequencyprecision clock source.

6 In essence, the reference clock frequency is divided down in a DDSarchitecture by the scaling factor set forth in a programmable binary tuning word. The tuningword is typically 24-48 bits long which enables a DDS implementation to provide superioroutput frequency tuning s cost-competitive, high-performance, functionally-integrated, and small package-sizedDDS products are fast becoming an alternative to traditional frequency-agile analog synthesizersolutions. The integration of a high-speed, high-performance, D/A converter and DDSarchitecture onto a single chip (forming what is commonly known as a Complete-DDS solution)enabled this technology to target a wider range of applications and provide, in many cases, anattractive alternative to analog-based PLL synthesizers.

7 For many applications, the DDS solutionholds some distinct advantages over the equivalent agile analog frequency synthesizer employingPLL advantages: Micro-Hertz tuning resolution of the output frequency and sub-degree phase tuningcapability, all under complete Digital control. Extremely fast hopping speed in tuning output frequency (or phase), phase-continuousfrequency hops with no over/undershoot or analog-related loop settling time anomalies. The DDS Digital architecture eliminates the need for the manual system tuning and tweakingassociated with component aging and temperature drift in analog synthesizer solutions. The Digital control interface of the DDS architecture facilitates an environment wheresystems can be remotely controlled, and minutely optimized, under processor control.

8 When utilized as a quadrature synthesizer, DDS afford unparalleled matching and control of Iand Q synthesized of OperationIn its simplest form, a direct Digital synthesizer can be implemented from a precision referenceclock, an address counter, a programmable read only memory (PROM), and a D/A converter (seeFigure 1-1).Copyright 1999 Analog Devices, 1-1. Simple Direct Digital SynthesizerIn this case, the Digital amplitude information that corresponds to a complete cycle of a sinewaveis stored in the PROM. The PROM is therefore functioning as a sine lookup table. The addresscounter steps through and accesses each of the PROM s memory locations and the contents (theequivalent sine amplitude words) are presented to a high-speed D/A converter.

9 The D/Aconverter generates an analog sinewave in response to the Digital input words from the output frequency of this DDS implementation is dependent on 1.) the frequency of thereference clock, and 2.) the sinewave step size that is programmed into the PROM. While theanalog output fidelity, jitter, and AC performance of this simplistic architecture can be quitegood, it lacks tuning flexibility. The output frequency can only be changed by changing thefrequency of the reference clock or by reprogramming the PROM. Neither of these optionssupport high-speed output frequency the introduction of a phase accumulator function into the Digital Signal chain, thisarchitecture becomes a numerically-controlled oscillator which is the core of a highly-flexibleDDS device.

10 As figure 1-2 shows, an N-bit variable-modulus counter and phaseFigure 1-2. Frequency-tunable DDS System register are implemented in the circuit before the sine lookup table, as a replacement for theaddress counter. The carry function allows this function as a phase wheel in the DDSarchitecture. To understand this basic function, visualize the sinewave oscillation as a vectorADDRESSCOUNTERSINELOOKUPREGISTERD/ ACONVERTERCLOCKN-BITSfCfOUTPHASEREGISTER P hase-to-AmplitudeConverterD/ACONVERTER SYSTEM CLOCKfOUTPHASE ACCUMULATOR24-48 BITSn14-16 BITSn-bit CarryTUNING WORDMC opyright 1999 Analog Devices, around a phase circle (see Figure 1-3). Each designated point on the phase wheelcorresponds to the equivalent point on aFigure 1-3.