Chapter 4 Electrical Characteristics of CMOS

1 Chapter 4 Electrical Characteristics of CMOSJin-Fu LiDepartment of Electrical EngineeringNational Central UniversityJungli, TaiwanAdvanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU2 Resistance & Capacitance Estimation DC Response Logic Level and Noise Margins Transient Response Delay Estimation Transistor Sizing Power Analysis Scaling TheoryOutlineAdvanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU3 Resistance , where is (resistivity, thickness, conductor length, conductor width) Sheet resistance Thus Resistance Estimation)/)(/(WLtR ),,,(WLt )/(WLRRs WWWLLLtt/ sR1 rectangular block)/(WLRRs 4 rectangular block)/()2/2(WLRWLRRss Advanced Reliable Systems (ARES) Lab.

2 Jin-Fu Li, EE, NCU4 A simplified linear model of MOS is useful at the logic level design RC model of an NMOS The drain-source resistance at any point on the current curve as shown belowDrain-Source MOS ResistanceDSCDCsRnGDSGVdsIdsabcAdvanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU5 Drain-Source Resistance The resistance at point a The current is approximated by Thus the resistance is The resistance at point b The full non-saturated current must be used so that Thus the resistance is )(/1tgsnnVVR dstgsndsVVVI)( ])(2[/2dstgsnnVVVR ])(2[212dsdstgsndsVVVVI Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU6 Drain-Source Resistance The resistance at point c The current is Thus the resistance is Rnis a function of both Vgsand Vds These equations show that it is not possible to define a constant value for Rn However, Rnis inversely proportion to in all cases, , , W/L is called aspect ratio2)(/2tgsndsnVVVR 2)(21tgsndsVVI nnR /1 )/(LWkn n Advanced Reliable Systems (ARES) Lab.

3 Jin-Fu Li, EE, NCU7 Capacitance Estimation The switching speed of MOS circuits are heavily affected by the parasitic capacitances associated with the MOS device and interconnection capacitances The total load capacitance on the output of a cmos gate is the sum of Gate capacitance Diffusion capacitance Routing capacitance Understanding the source of parasitic loads and their variations is essential in the design process Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU8 MOS-Capacitor Characteristics The capacitance of an MOS is varied with the applied voltages Capacitance can be calculated by is dielectric constant is permittivity of free space Depend on the gate voltage, the state of the MOS surface may be in Accumulation Depletion InversionAdCx 0 x 0 Consequently, the dynamic gate capacitance as a function of gate voltage, as shown below The minimum capacitance depends on the depth of the depletion region, which depends on the substrate doping densityAdvanced Reliable Systems (ARES) Lab.

4 Jin-Fu Li, EE, NCU9 MOS Capacitor Characteristics CoxVtVgCLow frequencyHigh frequencyAccumulationDepletionInversionA dvanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU10 MOS Device Capacitances The parasitic capacitances of an MOS transistor are shown as below Cgs, Cgd: gate-to-channel capacitances, which are lumped at the source and the drain regions of the channel, respectively Csb, Cdb: source and drain-diffusion capacitances to bulk Cgb: gate-to-bulk capacitanceCsbCdbCgdCgbCgsgatedepletion layersubstratesourcedrainCg=Cgb+Cgs+Cgdc hannelCsbCdbCgdCgbCgsAdvanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU11 Variation of Gate Capacitance The behavior of the gate capacitance in the three regions of operation is summarized as below Off region (Vgs<Vt): Cgs=Cgd=0; Cg=Cgb Non-saturated region (Vgs-Vt>Vds): Cgsand Cgdbecome significant.

5 These capacitances are dependent on gate voltage. Their value can be estimated as Saturated region (Vgs-Vt<Vds): The drain region is pinched off, causing Cgdto be zero. Cgs increases to approximately AtCCoxSiOgsgd2021 AtCoxSiOogs232 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU12 Approximation of the Cg The Cgcan be further approximated with , where The gate capacitance is determined by the gate area, since the thickness of oxide is associated with process of fabrication For example, assume that the thickness of silicon oxide of the given process is . Calculate the capacitance of the MOS shown belowoxSiOooxtC2 ACCoxg m 810150 2m 5 4 Advanced Reliable Systems (ARES) Lab.

6 Jin-Fu Li, EE, NCU13 Diffusion Capacitance Diffusion capacitance Cdis proportional to the diffusion-to-substrate junction area baSourceDiffusion AreaDrainDiffusion AreabaCjaXc (a finite depth)CjpSubstrate)22()(baCabCCjpjad Cja=junction capacitance per micron squareCjp=periphery capacitance per micronAdvanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU14 Junction Capacitance Semiconductor physics reveals that a PN junction automatically exhibits capacitance due to the opposite polarity chargesinvolved. This is called junctionor depletioncapacitance and is found at every drain or source region of a MOS The junction capacitance is varies with the junction voltage, it can be estimate as =junction voltage (negative for reverse bias) =zero bias junction capacitance ( ) =built-in junction voltagebVmbjjjVVCC )1( ~0 jVAdvanced Reliable Systems (ARES) Lab.

7 Jin-Fu Li, EE, NCU15 Single wire Capacitance Routing capacitance between metal and substrate can be approximated using a parallel-plate model In addition, a conductor can exhibit capacitance to an adjacent conductor on the same layerWLTF ringing fieldsHsubstrateInsulator (Oxide)Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU16 Multiple Conductor Capacitances Modern cmos processes have multiple routing layers The capacitance interactions between layers can become quite complex Multilevel-layer capacitance can be modeled as belowLayer 3 Layer 2 Layer 1C23C21C22C2=C21+C23+C22 Multi-layer conductorAdvanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU17A Process Cross Section Interlayer capacitances of a two-level-metal processBCADFGEm2m2m2m2m2m2m1m1m1 CCCCCCCCThin-oxide/diffusionSubstratepol ypolyAdvanced Reliable Systems (ARES) Lab.

8 Jin-Fu Li, EE, NCU18 For bond wire inductance For on-chip metal wires The inductance produces Ldi/dt noise especially for ground bouncing noise. Note that when cmos circuit are clocked, the current flow changes greatlyInductor)4ln(2dhL )48ln(2hwwhL dtdiLV hdhwAdvanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU19 Distributed RC Effects The propagation delay of a signal along a wire mainly depends on the distributed resistance and capacitance of the wire A long wire can be represented in terms of several RC sessions, as shown below The response at node Vjwith respect to time is then given by Vj-1 VjVj+1Ij-1 IjRCRCRCRCRCRVVRVVIIdtdVCIdtCdVjjjjjjj)( )()(111 Advanced Reliable Systems (ARES) Lab.

9 Jin-Fu Li, EE, NCU20 Distributed RC Effects As the number of sections in the network becomes large (and the sections become small), the above expression reduces to the differential form Alternatively, a discrete analysis of the circuit shown in the previous page yields an approximate signal delay of , where n=number of sections 222kxtdxVddtdVrcx cr: resistance per unit length: capacitance per unit length2)1( Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU21 wire Segmentation with Buffers To optimize speed of a long wire , one effective method is to segment the wire into several sections and insert buffers within these sections Consider a poly bus of length 2mm that has been divided into two 1mm sections.

10 Assume that With buffer Without buffer By keeping the buffer delay small, significant gain can be obtained with buffer insertion 215104xtx 21521510001041000104 bufpttbufbuftnsnstns 844nstp162000104215 Advanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU22 Crosstalk A capacitor does not like to change its voltage instantaneously. A wire has high capacitance to its neighbor. When the neighbor switches from 1-> 0 or 0->1, the wire tends to switch too. Called capacitive couplingor crosstalk. Crosstalk effects Noise on nonswitching wires Increased delay on switching wiresAdvanced Reliable Systems (ARES) Lab. Jin-Fu Li, EE, NCU23 Crosstalk Delay Assume layers above and below on average are quiet Second terminal of capacitor can be ignored Model as Cgnd= Ctop+ Cbot Effective Cadjdepends on behavior of neighbors Miller effectABCadjCgndCgndB VCeff(A)MCFC onstantVDDCgnd+ Cadj1 Switching with A0 Cgnd0 Switching opposite A2 VDDCgnd+ 2 Cadj2 Advanced Reliable Systems (ARES) Lab.