Training Course of Design Compiler [相容模式]

1 Training Course of Design Training Course of Design CompilerCompilerREF: CIC Training manual Logic Synthesis with Design Compiler , July, 2006 TSMC 0 18um Process 1 8-Volt SAGE-XTMS tand Cell Library Databook September 2003 T. W. Tseng, ARES Lab 2008 Summer Training Course of Design Compiler TSMC Process SAGE-XStand Cell Library Databook, September, 2003 TPZ973G TSMC Standard I/O Library Databook, Version 240a, December 10, 2003 Artisan User ManualSpeaker: T. J. ChenpAdvanced Reliable Systems (ARES) Basic Concept of the Synthesis Synthesis Using Design Compiler Synthesis Using Design CompilerAdvanced Reliable Systems (ARES) Concept of the SynthesisBasic Concept of the SynthesisAdvanced Reliable Systems (ARES) Design FlowMATLAB/ C/ C++/ System C/ ADS/ Covergen (MaxSim)Memory LevelADS/ Covergen (MaxSim)NC-Verilog/ ModelSimDebussy (Verdi)/ VCSV erilog/ VHDLS yntestRTL LevelDesign/ Power CompilerDFT Compiler / TetraMAXmpiler/ FusionConformal/FormalityLogic SynthesisDesign for TestNC-Verilog/ ModelSimDebussy (Verdi)

2 / VCShysical Comgma Blast Gate LevelSOC Encounter/ AstroDRC/ LVS (Calibre)PhMagGDS IILayout LevelPost-Layout VerificationPVS: Calibre xRC/ NanoSim(Time/ Power Mill)VerificationAdvanced Reliable Systems (ARES) Out4 What is Synthesis Synthesis = translation + optimization + mappingif(high_bits == 2 b10)beginresidue = state table[i];_[];endelse beginresidue = 16 h0000;endTranslate (HDL Compiler )HDL SourceHDL Source(RTL)Optimize + Mapping ( Design Compiler )No Timing Info.( Design Compiler )Generic Boolean(GTECT)Timing synthesis is constraint driven Advanced Reliable Systems (ARES) Technologyand technology independent !

3 !5 CompileRTL codeor netlistOptimized Design (Gate-Level Netlist)CompileAttributes &ConstraintsSchematicReports(Timing, Area, Power, .., etc)ConstraintsReportsFlattenTechnologyL ibStructure(g,, ,,)Logic Level OptimizationLibrary(Can be set by the GUI interface or user-defined Script File !!)Gate Level OptimizationMapTechnologyLibraryAdvanced Reliable Systems (ARES) Verilog Verilog Basis parameter declarationsp wire, wand, wor declarations reg declarations input output inout declarations input, output, inout declarations continuous assignments module instructions gate instructions always blocks task statements task statements function definitions for, while loop Synthesizable Verilog primitives cells and, or, not, nand, nor, xor, xnor bufif0, bufif1, notif0, notif1 Advanced Reliable Systems (ARES) Lab.

4 ,,,7 Synthesizable Verilog (Cont ) Operators Binary bit-wise ( ~, &, |, ^, ~^)y(|) Unary reduction ( &, ~&, |, ~|, ^, ~^) Logical ( !, &&, ||) 2 s complement arithmetic (+*/%) 2s complement arithmetic ( +, -, , /, %) Relational ( >, <, >=, <=) Equality ( ==, !=) Logic shift ( >>, <<) Conditional ( ?:) Concatenation ({}) Concatenation ( { })Advanced Reliable Systems (ARES) Before Synthesis Your RTL designAreaCycleBetter Functional verification by some high-level language Also, the code coverage of your test benches should be verified ( VN) Coding style checking ( n-Lint)Time Coding style checking ( nLint)

5 Good coding style will reduce most hazards while synthesis Better optimization process results in better circuit performance Edbi fhi Easy debugging after synthesis Constraints The area and timing of your circuit are mainly determined by your The area and timing of your circuit are mainly determined by your circuit architecture and coding style There is always a trade-off between the circuit timing and area In fact, a super tight timing constraint may be worked while synthesis, but failed in the Place & Route (P&R) procedureAdvanced Reliable Systems (ARES) Using Design CompilerSynthesis Using Design CompilerAdvanced Reliable Systems (ARES) Compiler setup fileGTLypy_pgp script model of standard cellsEx:Advanced Reliable Systems (ARES) <.

6 > File link_library: the library used for interpreting input description Any cells instantiated in your HDL code Wire load or operating condition modules used during synthesis target_library: the ASIC technology which the Design is mapped symbol library: used for schematic generation symbol_library: used for schematic generation search_path: the path for unsolved reference library synthetic_path: designware libraryy_pgyAdvanced Reliable Systems (ARES) <. > File (Cont ) MEMs libraries are also included in this fileEx:Add a search path MEM Libraries (.db file)(. File)(y py_p)Note that the MEM DB filesare converted fromtheLIB fileswhich are generated from the Artisan !

7 !Advanced Reliable Systems (ARES) LIB fileswhich are generated from the Artisan !!13 Settings for Using Memory Convert *.lib to *.db %> dc shell tany memory LIB file %> dc_shell t dc_shell-t> read_lib dc_shell-t> write_lib t13spsram512x32-output \ Modify <. > File: *user library name, which shouldbe the same as the library namein the Artisan set link_library * set target library slow dbt13spsram512x32 slow db memory DB fileadd to the file set target_library add a search path to this file Before the synthesis, the memory HDL model should be y,yblocked in your netlistAdvanced Reliable Systems (ARES)

8 FlowDFT InsertionDesign ImportSetting Design EnvironmentSetting Clock Compile AfterDFTA ssign ViolationSetting Clock ConstraintsSetting Design Assign ViolationAvoidanceNaming RuleRule ConstraintsCompile the DesignChangingSave DesignDesignAdvanced Reliable Systems (ARES) Started Prepare Files: *.v files *.db files ( memory is used)Shi ifil(id ibdl ) Synthesis script file ( described later) linux %> dv& (XG Mode)Tool BarLogic HierarchyLogic Hierarchy ViewLog Window(GUI view of the Design Vision)Command LineAdvanced Reliable Systems (ARES) Lab.(g)16 Read FileDesign Import Read netlists or other Design descriptions into Design Compiler File/Read Supported formats Verilog.

9 V VHDL: .vhd System Verilog: .sv EDIF PLA (Berkeley Espresso): .pla Synopsys internal formats: DB (binary): db DB (binary): .db Enhance db file: .ddc Equation: .eqn State table: st State table: .stread file format verilog file name{ Command Line }Advanced Reliable Systems (ARES) format verilog file name17 PAD Parameters Extraction Input PAD Input delaypy Input driving Output PAD Ot tdl Output delay Output loadingCHIP (delay, loading)(delay, driving)( ){ Command Line } CHIP characterize [get_cells CORE]current_design CORE write script format dctcl o chip Reliable Systems (ARES) format dctcl o Select the most top Design of the hierarchy Hierarchy/Uniquify/Hierarchyuniquify{ Command Line }( Design View)(Log Window)

10 Advanced Reliable Systems (ARES) EnvironmentSetting Design Environment Setting Operating Environment Setting Input Driving Strength Setting Input Driving Strength Setting Output Loading Setting Input/Output Delay Setting Input/Output Delay Setting Wire Load ModelAdvanced Reliable Systems (ARES) Operating Condition Attributes/Operating Environment/Operating ConditionsSetup/Hold time is evaluatedset_operating_conditions max slow max_library slow min fast \-min library fast { Command Line }Advanced Reliable Systems (ARES) fast21 Setting Drive Strength/Input Delay for PADs Assume that we use the input PAD PDIDGZ my designPADCFFQDbInput PAD(PDIDGZ)(PDIDGZ)set_drive [expr ] [all_inputs]set input delay[ ] clock clk[all inputs]{ Command Line }Advanced Reliable Systems (ARES) [p][_p]22 Setting Load/Output Delay for PADs Assume that we use the output PAD PDO24 CDG my designFFQD dclkOutput PADPADI(PDO24 CDG)clkOEN(PDO24 CDG)set_load [expr ] [all_outputs]set_output_delay [expr 2] [all_outputs]{ Command Line }Advanced Reliable Systems (ARES)