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My Hspice 教學 - NCU

HSPICESo rce :JhHe LinSource : Jh-He LinSpeaker Jh-He LinDesign Flow DeclarationVlS Voltage Source Circuit StatementsSbiit Sub-circuit MeasuresOti Operation OthersChih-Sheng HouAdvancedReliableSystemLabARESLabDecla ration (1/2) **example of inverter 1** .LIB ' ' ttVdd .GLOBAL Vdd .TRAN 1ns 1000ns .OPTION post **voltage source**Mp1Mp2x **voltage source** Vsourece Vdd 0 Vsignal in 0 pulse( 0 0ns 5ns 5ns 95ns 200ns) ** circuit statement**Mp2Mn1inout Mp1 x in Vdd Vdd pch L= W= M=1 Mn1 x in 0 0 nch L= W= M=1 Mp2 out x VddVddpch L= W= M=1 Mn2 out x 0 0 nch L= W= M=1 **measure** MEAS TRANout rise delayTRIG v(in) VAL=0 9v TD=0 FALL=3 TARG v(x) VAL=0 9v RISE=3 .MEAS TRAN out_rise_delayTRIG v(in) VAL= TD=0 FALL=3 TARG v(x) VAL= RISE=3 .MEAS TRAN pwr AVG POWER .ENDD eclaration (2/2).

Mn1 x in 0 0 nch L=0.18u W=0.22u M=1 Mp2 out ... .ENDSNodes are assigned by using BULK=node in MOSFET or BJT models • Param is used only in sbucircuit and it can be overridden by subckt call or values in .PARAM statement

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Transcription of My Hspice 教學 - NCU

1 HSPICESo rce :JhHe LinSource : Jh-He LinSpeaker Jh-He LinDesign Flow DeclarationVlS Voltage Source Circuit StatementsSbiit Sub-circuit MeasuresOti Operation OthersChih-Sheng HouAdvancedReliableSystemLabARESLabDecla ration (1/2) **example of inverter 1** .LIB ' ' ttVdd .GLOBAL Vdd .TRAN 1ns 1000ns .OPTION post **voltage source**Mp1Mp2x **voltage source** Vsourece Vdd 0 Vsignal in 0 pulse( 0 0ns 5ns 5ns 95ns 200ns) ** circuit statement**Mp2Mn1inout Mp1 x in Vdd Vdd pch L= W= M=1 Mn1 x in 0 0 nch L= W= M=1 Mp2 out x VddVddpch L= W= M=1 Mn2 out x 0 0 nch L= W= M=1 **measure** MEAS TRANout rise delayTRIG v(in) VAL=0 9v TD=0 FALL=3 TARG v(x) VAL=0 9v RISE=3 .MEAS TRAN out_rise_delayTRIG v(in) VAL= TD=0 FALL=3 TARG v(x) VAL= RISE=3 .MEAS TRAN pwr AVG POWER .ENDD eclaration (2/2).

2 LIB ' ' tt Using 0 18 technology to design Using technology to design tt : typical model for devices .GLOBAL Vdd .TRAN 1ns 1000ns .OPTION post1000nsVoltage Source (1/4) **example of inverter 1** .LIB ' ' ttVdd .GLOBAL Vdd .TRAN 1ns 1000ns .OPTION post **voltage source**Mp1Mp2x voltage source Vsourece Vdd 0 Vsignal in 0 pulse( 0 0ns 5ns 5ns 95ns 200ns) ** circuit statement**Mp2Mn1inout Mp1 x in Vdd Vdd pch L= W= M=1 Mn1 x in 0 0 nch L= W= M=1 Mp2 out x VddVddpch L= W= M=1 Mn2 out x 0 0 nch L= W= M=1 **measure** MEAS TRANout rise delayTRIG v(in) VAL=09vTD=0 FALL=3 TARG v(x) VAL=0 9v RISE=3 .MEAS TRAN out_rise_delayTRIG v(in) VAL TD 0 FALL 3 TARG v(x) VAL RISE 3 .MEAS TRAN pwr AVG POWER .ENDV oltage Source (2/4) Syntax Vxxxn+ n<<DC=>dcval>Vxxxn+ n-<<DC=>dcval>Iyyy n+ n- <<DC=>dcval> ExampleV1 node1 0 DC=5vV2 d 205V2 node2 0 5vI3 node3 0 3mAVoltage Source (3/4) Pulse source function: PULSE St SyntaxPULSE( V1 V2 Tdelay Trise Tfall duty_cycle_width Period ) ExampleV1 node1 node2 PULSE ( 0V 5V 0ns 10ns 10ns 40ns 100ns)5V2 node3 node4 PULSE( 5V 0V 0ns 10ns 10ns 40ns 100ns)1020304050607080901001101201300102 03040506070809010011012013050 Chih-Sheng HouAdvancedReliableSystemLabARESLabVolta ge Source (4/4) Piecewise linear source function: PWL Syntax SyntaxPWL(t1 v1, t2 v2, ) ExampleV1 node1 0 PWL(0n 0v, 20n 0v, 21n 3v, 25n 3v, 26n 0v,30n 0v)Chih-Sheng HouAdvancedReliableSystemLabARESLabCircu it Statements (1/5) **example of inverter 1**.

3 LIB ' ' ttVdd .GLOBAL Vdd .TRAN 1ns 1000ns .OPTION post **voltage source**Mp1Mp2x voltage source Vsourece Vdd 0 Vsignal in 0 pulse( 0 0ns 5ns 5ns 95ns 200ns) ** circuit statement**Mp2Mn1inout Mp1 x in Vdd Vdd pch L= W= M=1 Mn1 x in 0 0 nch L= W= M=1 Mp2 out x VddVddpch L= W= M=1 Mn2 out x 0 0 nch L= W= M=1 **measure** MEAS TRANout rise delayTRIG v(in) VAL=09vTD=0 FALL=3 TARG v(x) VAL=0 9v RISE=3 .MEAS TRAN out_rise_delayTRIG v(in) VAL TD 0 FALL 3 TARG v(x) VAL RISE 3 .MEAS TRAN pwr AVG POWER .ENDC ircuit Statements (2/5) Instance and element names CCapacitorCxxxNode1 Node2 Value CCapacitor DDiode E,F,G,HDependent current and voltage controlled sourceCxxxNode1 Node2 Va l u e ICurrent JJFET or MESFET KMutual inductorIxxx Node1 Node2 ValueKMutual inductor LInductor MMOSFETLxxx Node1 Node2 ValueMxxx D G S B Type L=val W=val M=val QBJT RResistor O,T,UTransmission lineRxxx Node1 Node2 Value,, VVoltage source XSubcircuit callVxxx Node1 Node2 ValueChih-Sheng HouAdvancedReliableSystemLabARESLabCircu it Statements (3/5) Units Oh*R i t H*I d t Ohm*Resistance Farad*Capacitor Henry*Inductor Scales T1012 M10-3 G109 Meg1063 U10-6 N10-912 K103 P10-12 F10-15 Chih-Sheng HouAdvancedReliableSystemLabARESLabCircu it Statements (4/5)

4 MOSFET element St Syntax Mxxx nd ng ns nbmname<L=val> <W=val> <M=val> ExampleM0 d0 g0 s0 b0 nch L= W= M=1M1d1g1s1b1pchL018W022M4M0M1M1 d1 g1 s1 b1 pchL= W= M=4 DSNMOSPMOSM0M1 GGBBDSChih-Sheng HouAdvancedReliableSystemLabARESLabCircu it Statements (5/5)**resistance R **R1node1 node210kR1node1 node2 10k**voltage source V **R 10knode_1V4node3 node4 1vR=10knode_2**capacitor C **C2node2 node4 10pnode_3C=10p**MOS M **M3node2 node3 node4 node4 VpV=1+ nch W= L= M=1node_4 Chih-Sheng HouAdvancedReliableSystemLabARESLabSUBCK T of Circuit Statement(1/3) .SUBCKT statement SUBCKTbNd1<Nd2 > .SUBCKT subnameNode1 <Node2 .. > The following are not included in node Ground node (0) Nodes are assigned by .GLOBAL statement .ENDSN odes are assigned by using BULK=node in MOSFET or BJT models Param is used only in sbucircuit and it can be overridden by subckt callyyor values in.

5 PARAM statementSbi illl Subcircuitcalls n1 <n2 n3 ..> SubcktName <param=val ..> <M=val>.Xadd1 n1 n2 n3 n4 n5 FA WN=3u LN=1u M= 1 2 3 4 nos Wsize= Lsize= M=2W=WNChih-Sheng HouAdvancedReliableSystemLabARESLabWWNSU BCKT of Circuit Statement(2/3) **SUBCKT statement** .SUBCKT inverter inv invb Mp0 invb inv VddVddpch L= W= M=1 Mn0 invb inv 0 0 nch L= W= M=1 .ENDS inverter **circuit statement**Mp0SB **circuit statement** Xinv1 in x inverter Xinv2 x out inverterMp0invinvbDGMn0 VddSBMp1Mp2xinoutMp2Mn1 SUBCKT of Circuit Statement(3/3) ** circuit statement** SUBCKT inverter invinvb .SUBCKT inverter inv invb Mp1 x in Vdd Vdd pch L= W= M=1 Mn1 x in 0 0 nch L= W= M=1 Mp2 out xVddVddpchL=0 18u W=0 44u M=1 Mp2 out x VddVddpchL= W= M=1 Mn2 out x 0 0 nch L= W= M=1 **SUBCKT statement**iiib.

6 SUBCKT inverter inv invb Mp0 invb inv Vdd Vdd pch L= W= M=1 Mn0 invb inv 0 0 nch L= W= M=1 .ENDS inverter **circuit statement** Xinv1 in x inverter Xinv2 x out inverterMeasures (1/4) **example of inverter 2** .LIB ' ' tt OPTION postVddVddinv1inv1 .OPTION post .GLOBAL Vdd .TRAN 1ns 1000ns **voltage source**VVdd018Mp1Mp2x VsoureceVdd0 Vsignal in 0 pulse( 0 0ns 5ns 5ns 95ns 200ns) **SUBCKT statement** .SUBCKT inverter inv invb0ibiddddh0 180 661Mp2Mn1xinout Mp0 invbinv VddVddpchL= W= M=1 Mn0 invb inv 0 0 nch L= W= M=1 .ENDS inverter **circuit statement** Xinv1 in x inverter Xinv2 x out inverter **measure** .MEAS TRAN out_rise_delay TRIG v(in) VAL= TD=0 FALL=3 TARG v(x) VAL= RISE=3 .MEAS TRAN pwr AVG POWER .ENDM easures (2/4) Syntax MEASURETRAN resultTRIGTARG .MEASURETRAN result result:name is given the measured value in Hspice output :TRIG trig_varVAL=trig_value <TD=time_delay> <RISE=n> +<FALL=n>.

7 TRAN power AVG POWER Example .MEASTRAN result1 TRIGv(in) VAL=2vRISE=2 TARGv(out) VAL= FALL=1 .MEAS TRANpwrAVG POWER Chih-Sheng HouAdvancedReliableSystemLabARESLabMeasu res (3/4) **measure** .MEAS TRAN out_rise_delay TRIG v(in) VAL= TD=0 FALL=3 TARG v(x) VAL= RISE=3 FALL=3 FALL=2 FALL=1 RISE=1 RISE=2 RISE=3 RISE=1 RISE=2 RISE=3 Measure (4/4) .MEAS TRAN pwr AVG POWER END .ENDO peration (1/3) .OPTION post Cti t0 filtif Creating a .tr0 file to view waveformStep 1 Step 2 Step 2 Step 3 Operation (2/3)Step 4 Step 5 Step 6 Operation (3/3)Others Minimum width size is (in meter) Minimum length size is (in meter) Capital and lowercase are equivalence in HSPICEpq 0 and GND are equivalence VsoureceVdd018v VsoureceVdd0 Vsourece Vdd GND Source Source : Speaker : IP (NIS) (NFS) vi vi vi filename vi vi x(X) ( ) i ( ) a ( )x(X) ( ) dd v ( )a ( ) o [Esc] y (yy ) p u Ctrl+r 30 cd mkdir ls file rmdir directory pwd ps cp kill tar mv tar passwd rm 31 (1/12) cd d cdxxx xxx cd.

8 Cd / 32 (2/12) ls33 (3/12) pwd 34 (4/12) cp cp cp cp cp /usr3 ~/document/cp /usr3 . cp / cp / cp /usr3 ~/ cp -r /cp -r /usr3/tf/ ~/document/cp -r /usr3/tf/ ~/document/035tf/ 35 (5/12) mv mv mv / ~/ mv fld /k/mvfolder/ work/ mv / / mvfolder/ ~/document/work/36 (6/12) rm rm ~/ rm -r rm -r ~/document/37 (7/12) Mkdir kdi mkdir mkdirtempmkdirtemp 34mkdirtemp_34mkdirtemp-34 ( ) mkdir / mkdir/temp/mkdir~/temp/38 (8/12) rmdir di rmdir rmdirtemprmdirtemp 34rmdirtemp_34 rmdir / rmdir~/temp/39 (9/12) ps40 (10/12) kill kill PID( ) kill PID( )41 (11/12)

9 Tar tf tar -cvf tar ~/document/ tar -cvf / tar -cvf~/ ~/document/ tarf tar -xvf tar 42 (12/12) passwd 43 Operation (1/8)44 Operation (2/8)45 Operation (3/8)46 Operation (4/8)47 Operation (5/8)48 Operation (6/8)Step 1 Step 2 Step 2 Step 3 Operation (7/8)Step 4 Step 5 Step 6 Operation (8/8)


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