Chip Scale PAL/NTSC Video Encoder with …

1 Chip Scale PAL/NTSC Video Encoder with advanced power Management Data Sheet ADV7174/ADV7179. FEATURES Programmable subcarrier frequency and phase ITU-R1 BT601/BT656 YCrCb to PAL/NTSC Video Encoder Programmable LUMA delay High quality 10-bit Video DACs Individual on/off control of each DAC. SSAF (super sub-alias filter) CCIR and square pixel operation advanced power management features Integrated subcarrier locking to external Video source CGMS (copy generation management system) Color signal control/burst signal control WSS (wide screen signaling) Interlaced/noninterlaced operation ntsc M, PAL N2, PAL B/D/G/H/I, PAL-M3 , PAL 60 Complete on-chip Video timing generator Single 27 MHz clock required ( 2 oversampling) Programmable multimode master/slave operation Macrovision (ADV7174 only) Closed captioning support 80 dB Video SNR Teletext insertion port (PAL-WST).

2 32-bit direct digital synthesizer for color subcarrier On-board color bar generation Multistandard Video output support: On-board voltage reference Composite (CVBS) 2-wire serial MPU interface (I2C compatible and fast I2C). Component S- Video (Y/C) Single-supply V and V operation Video input data port supports: Small 40-lead 6 mm 6 mm LFCSP package CCIR-656 4:2:2 8-bit parallel input format 40 C to +85 C at V. Programmable simultaneous composite and S- Video or RGB 20 C to +85 C at V. (SCART)/YPbPr Video outputs Qualified for automotive applications Programmable luma filters low-pass [ PAL/NTSC ] notch, APPLICATIONS. extended SSAF, CIF, and QCIF. Portable Video applications Programmable chroma filters (low-pass [ MHz, MHz, Mobile phones MHz, and MHz], CIF, and QCIF).

3 Digital still cameras Programmable VBI (vertical blanking interval). FUNCTIONAL BLOCK DIAGRAM. TTXREQ TTX. ADV7174/ADV7179 M. power 10 U 10. MANAGEMENT CGMS AND WSS TELETEXT L 10-BIT DAC A (PIN 29). CONTROL INSERTION INSERTION T DAC. VAA YUV TO 10. (SLEEP MODE) BLOCK BLOCK RBG I 10. MATRIX P 10-BIT. DAC DAC B (PIN 28). L. RESET 10 E 10. X 10-BIT. E DAC DAC C (PIN 24). COLOR 8 Y 8 ADD 9 INTER- 9 PROGRAMMABLE 10 R. DATA SYNC POLATOR LUMINANCE. 4:2:2 TO YCrCb FILTER. P7 P0 4:4:4 8 TO U 8 8 8 10 U. INTER- YUV. POLATOR MATRIX ADD INTER- PROGRAMMABLE. V 8 BURST 8 POLATOR 8 CHROMINANCE 10. 8 FILTER V. HSYNC 10 10. Video TIMING. FIELD/VSYNC GENERATOR REAL-TIME VREF. SIN/COS VOLTAGE. BLANK I2C MPU PORT CONTROL DDS BLOCK REFERENCE RSET. CIRCUIT CIRCUIT COMP.

4 02980-A-001. CLOCK SCLOCK SDATA ALSB SCRESET/RTC GND. Figure 1. 1. ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations). 2. Throughout the document, N is referenced to PAL Combination N. 3. ADV7174 only. The Macrovision anticopy process is licensed for noncommercial home use only, which is its sole intended use in the device. Contact the sales office for the latest Macrovision version available. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice.

5 No One Technology Way, Box 9106, Norwood, MA 02062-9106, license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 2002 2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support ADV7174/ADV7179 Data Sheet TABLE OF CONTENTS. Features .. 1 Timing Mode Register 0 (TR0) .. 33. Applications .. 1 Timing Mode Register 1 (TR1) .. 34. Functional Block Diagram .. 1 Subcarrier Frequency Registers 3 0 .. 35. Revision History .. 3 Subcarrier Phase Register .. 35. 4 Closed Captioning Even Field Data Registers 1 0 .. 35. V Specifications .. 4 Closed Captioning Odd Field Data Registers 1 0 .. 36. V Timing Specifications.

6 5 ntsc Pedestal/PAL Teletext Control Registers 3 0 .. 36. V Specifications .. 6 Teletext Request Control Register (TC07) .. 37. V Timing Specifications .. 7 CGMS_WSS Register 0 (C/W0) .. 37. Absolute Maximum 9 CGMS_WSS Register 1 (C/W1) .. 38. ESD Caution .. 9 CGMS_WSS Register 2 (C/W2) .. 38. Pin Configuration and Function Descriptions .. 10 Appendix 1 Board Design and Layout Considerations .. 39. General Description .. 11 Ground Planes .. 39. Data Path 11 power Planes .. 39. Internal Filter Response .. 11 Supply Decoupling .. 40. Typical Performance Characteristics .. 13 Digital Signal Interconnect .. 40. Features .. 16 Analog Signal 40. Color Bar Generation .. 16 Appendix 2 Closed Captioning .. 41. Square Pixel Mode .. 16 Appendix 3 Copy Generation Management System Color Signal Control.

7 16 (CGMS).. 42. Burst Signal Control .. 16 Function of CGMS Bits .. 42. ntsc Pedestal Control .. 16 Appendix 4 Wide Screen Signaling (WSS) .. 43. Pixel Timing Description .. 16 Function of WSS Bits .. 43. Subcarrier Reset .. 16 Appendix 5 44. Real-Time Control .. 16 Teletext Insertion .. 44. power -On Reset .. 25 Teletext Protocol .. 44. SCH Phase Mode .. 25 Appendix 6 Waveforms .. 45. MPU Port Description .. 25 ntsc Waveforms ( with Pedestal) .. 45. Register Accesses .. 26 ntsc Waveforms (without Pedestal).. 46. Register Programming .. 27 PAL Waveforms .. 47. Subaddress Register (SR7 SR0).. 27 Pb Pr Waveforms .. 48. Register Select (SR5 SR0) .. 27 Appendix 7 Optional Output Filter .. 49. Mode Register 1 (MR1) .. 29 Appendix 8 Recommended Register Values.

8 50. Mode Register 2 (MR2) .. 30 Outline Dimensions .. 52. Mode Register 3 (MR3) .. 31 Ordering Guide .. 52. Mode Register 4 (MR4) .. 32 Automotive Products .. 52. Rev. C | Page 2 of 52. Data Sheet ADV7174/ADV7179. REVISION HISTORY. 1/15 Rev. B to Rev. C. Updated Outline Dimensions ..52. Changes to Ordering Guide ..52. 4/09 Rev. A to Rev. B. Changes to power -On Reset Section ..25. Changes to Figure 55 ..40. Changes to Figure 69, Figure 70, and Figure 72 ..47. Changes to Figure 81 Caption ..52. Changes to Ordering Guide ..52. 2/04 Changed from Rev. 0 to Rev. A. Added V Version .. Universal Format Universal Device Currents Updated on V Specification .. Universal Added new Table 1 and renumbered Subsequent 4. Added new Table 2 and Renumbered Subsequent Tables.

9 5. Change to Figure 54 ..38. Change to Figure 55 ..39. Change to Figure 79 ..48. Changed Ordering Guide Temperature Specifications ..52. Updated Outline Dimensions ..52. 10/02 Revision 0: Initial Version Rev. C | Page 3 of 52. ADV7174/ADV7179 Data Sheet SPECIFICATIONS. V SPECIFICATIONS. VAA = V, VREF = V, RSET = 150 . All specifications TMIN to TMAX1, unless otherwise noted. Table 1. Parameter Conditions1 Min Typ Max Unit STATIC PERFORMANCE2. Resolution (Each DAC) 10 Bits Accuracy (Each DAC). Integral Nonlinearity RSET = 300 LSB. Differential Nonlinearity Guaranteed monotonic 1 LSB. DIGITAL INPUTS2. Input High Voltage, VINH V. Input Low Voltage, VINL V. Input Current, IIN VIN = V or V 1 A. Input Capacitance, CIN 10 pF. DIGITAL OUTPUTS2.

10 Output High Voltage, VOH ISOURCE = 400 A V. Output Low Voltage, VOL ISINK = mA V. Three-State Leakage Current 10 A. Three-State Output Capacitance 10 pF. ANALOG OUTPUTS2. Output Current 3 RSET = 150 , RL = 33 37 mA. DAC-to-DAC Matching %. Output Compliance, VOC 0 V. Output Impedance, ROUT 30 k . Output Capacitance, COUT IOUT = 0 mA 30 pF. power REQUIREMENTS2, 4. VAA V. Normal power Mode IDAC (Max)5 RSET = 150 , RL = 115 120 mA. ICCT6 30 mA. Low power Mode IDAC (Max)5 62 mA. ICCT6 30 mA. Sleep Mode IDAC7 A. ICCT8 A. power Supply Rejection Ratio COMP = F %/%. 1. Temperature range TMIN to TMAX: 20 C to +85 C. 2. Guaranteed by characterization. 3. DACs can output 35 mA typically at V (RSET = 150 and RL = ). Full drive into load. 4. power measurements are taken with clock frequency = 27 MHz.