直接数字频率合成(DDS)基本原理 - Analog Devices

1 MT-085 (DDS) fcADDRESSCOUNTERSINLOOKUPTABLEN-BITSCLOC KREGISTERLPFDAC foutLOOKUP TABLE CONTAINS SINEDATA FOR INTEGRAL NUMBEROF CYCLESN-BITSfcADDRESSCOUNTERSINLOOKUPTAB LEN-BITSCLOCKREGISTERLPFDAC foutLOOKUP TABLE CONTAINS SINEDATA FOR INTEGRAL NUMBEROF CYCLESN-BITS 1 , 10/08, WK Page 1 of 9 DDS (DDS) 1 ( ) (PROM) DAC DAC DDS DAC PLL MT-085fcSERIALOR BYTELOADREGISTERnnFREQUENCY CONTROLPHASEREGISTERLPFDACPARALLELDELTAP HASEREGISTERMCLOCKnnPHASE ACCUMULATORnPHASETRUNCATION12-19 BITSAMPLITUDETRUNCATION2n=foM fcN-BITSn = 24 - 48 BITSPHASE-TOAMPLITUDECONVERTERM = TUNING WORDSYSTEM CLOCK(10-14) 2 DDS Page 2 of 9 DDS PROM DDS (NCO) 2 M 32 232( 40 )

2 ( ) 0 360 ( 90 MSB ) DAC 3 MT-085n8121620242832482n=foM fcNumber of Points = 2n2564,09665,5361,048,57616,777,216268,4 35,4564,294,967,296281,474,976,710,656M = JUMP SIZE 3 Page 3 of 9 n = 32 M = 1 232 232 M=2 n ( DDS n 24 32) 2n M fc DDS fc/2n n = 32 40 DDS 13 15 MSB ( 4) 1 MT-085 NORMALIZED FREQUENCY - 4 15 90 dB SFDRPage 4 of 9 DAC 2 4 N DAC 4 32 15 M DAC 90 dB 12 DAC DDS M DDS M DDS DDS ( ) 1/3 5 DDS DAC 30 MHz 100 MHz DAC (100 30 = 70 MHz) MT-085 5 DDS Page 5 of 9 DAC ( ) sin(x)

3 /x A(fO) fO fc DAC ( ) sin(x)/x dB(DAC 1/2) sin(x)/x DAC ( 1/3 ) PLL DDS 100 MHz 30 MHz 30 MHz 60 MHz( ) 100 60 = 40 MHz( ) (90 MHz) 100 90 = 10 MHz 120 100 MHz = 20 MHz ( fc/2) 4 2MT-085 6 DDS ADC .DAC OUTPUT125 MHzCMOS ADCCLOCK 100k 42 MHz200 LPF100k 470pF100 -+200 Page 6 of 9 ADC DDS DDS ( AD9850) ADC ADC ( 6) DAC IOUT 200 42 MHz 100 42 MHz AD9850 DAC 100 100 k 2 ns TTL/CMOS 20 ps rms 6 40 MSPS ADC 50 ps rms DDS DDS DAC 7 DAC DAC AD9850 1 MHz +1 V MT-085fcPHASEACCUMULATORNSINLOOKUPTABLED ACAMREGISTERNMULTIPLIEROUTPUTVREF 7 DDS Page 7 of 9 DDS DDS DAC N DAC DDS DAC q/ 12( q LSB )

4 DDS ( ADC ADC ) DAC SFDR 8 4096 (4k) FFT 12 DAC (A) 40 SFDR 77 dBc SFDR 94 dBc SFDR 17 dB MT-085(A) fOUT= MHz, fS= MHz(B) fOUT= MHz, fS= MHzFFT SIZE = 8192 SFDR = 77dBcSFDR = 94dBcTHEORETICAL 12-BIT SNR = 74dBFFT PROCESS GAIN = 36dBFFT NOISE FLOOR = 110dBFS 8 4096 FFT 12 DAC SFDR fcDACMVN = rmsPSEUDORANDOMNUMBERPHASEACCUMU-LATORDE LTAPHASEREGISTERSINELOOKUPTABLEADDERq2 GENERATOR 9 DDS SFDRPage 8 of 9 SFDR ADC DDS 9 ( 8 9 10) DDS DAC 1/2 LSB DDS Page 9 of 9 MT-085 The Application Engineer 33: All About Direct Digital Synthesis ( Analog Dialogue, Vol.)

5 38, August 30, No. 32004). 2."Single-Chip Direct Digital Synthesis vs. the Analog PLL," ( Analog Dialogue, Vol., 1996. Design, By David Brandon, EDN, May 13, 2004. Technical Tutorial on Digital Signal Synthesis, 1999, Analog Devices , Inc..5Di rect Digital Synthesis Frequently Asked Questions, Analog Devices , Inc. Buchanan, "Choosing DACs for Direct Digital Synthesis," Application Note AN-237, Analog Devices , Inc. Brandon, "Direct Digital Synthesizers in Clocking Applications," Application Note AN-823, Analog Devices , 2006. J. Kerr and Lindsay A. Weaver, "Pseudorandom Dither for Frequency Synthesis Noise," Patent 4,901,265, filed December 14, 1987, issued February 13, 1990. T. Nicholas, III and Henry Samueli, "An Analysis of the Output Spectrum of Direct Digital Frequency Synthesizers in the Presence of Phase-Accumulator Truncation," IEEE 41st Annual Frequency Control Symposium Digest of Papers, 1987, pp.

6 495-502, IEEE Publication No. CH2427-3/87/0000-495. he Optimization of Direct Digital Frequency Synthesizer Length Effects," IEEE 42nd Annual Frequency Control Symposium Digest of Papers," 1988, pp. 357-363, IEEE Publication No. CH2588- 2/88/0000-357. T. Nicholas, III and Henry Samueli, "TPerformance in the Presence of Finite Word design tool from Analog Devices . 12. Hank Zumbahlen, Basic Linear Design, Analog Devices , 2006, ISBN: 0-915550-28-1. Also available as Li near Circuit Design Handbook, Elsevier-Newnes, 2008, ISBN-10: 0750687037, ISBN-13: 978-0750687034. Chapter 4. 13. Walt Kester, Analog -Digital Conversion, Analog Devices , 2004, ISBN 0-916550-27-3, Chapter 6. Also available as The Data Conversion Handbook, Elsevier/Newnes, 2005, ISBN 0-7506-7841-0, Chapter 6.

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