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Dual 4-input AND gate - Nexperia

74HC21 Dual 4-input AND gateRev. 9 2 May 2023 Product data sheet1. General descriptionThe 74HC21 is a dual 4-input AND gate. Inputs include clamp diodes. This enables the use ofcurrent limiting resistors to interface inputs to voltages in excess of Features and benefits Wide supply voltage range from to V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B CMOS input levels Complies with JEDEC standards: JESD8C ( V to V) JESD7A ( V to V) ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and from -40 C to +125 Ordering informationTable 1. Ordering informationPackageType numberTemperature rangeNameDescriptionVersion74HC21D-40 C to +125 CSO14plastic small outline package; 14 leads;body width mmSOT108-174HC21PW-40 C to +125 CTSSOP14plastic thin shrink small outline package; 14 leads;body width mmSOT402-14.

Nexperia 74HC21 Dual 4-input AND gate 10. Dynamic characteristics Table 7. Dynamic characteristics GND = 0 V; test circuit see Fig. 8. Symbol Parameter Conditions 25 °C -40 °C to +85 °C -40 °C to +125 °C

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Transcription of Dual 4-input AND gate - Nexperia

1 74HC21 Dual 4-input AND gateRev. 9 2 May 2023 Product data sheet1. General descriptionThe 74HC21 is a dual 4-input AND gate. Inputs include clamp diodes. This enables the use ofcurrent limiting resistors to interface inputs to voltages in excess of Features and benefits Wide supply voltage range from to V CMOS low power dissipation High noise immunity Latch-up performance exceeds 100 mA per JESD 78 Class II Level B CMOS input levels Complies with JEDEC standards: JESD8C ( V to V) JESD7A ( V to V) ESD protection: HBM JESD22-A114E exceeds 2000 V MM JESD22-A115-A exceeds 200 V Specified from -40 C to +85 C and from -40 C to +125 Ordering informationTable 1. Ordering informationPackageType numberTemperature rangeNameDescriptionVersion74HC21D-40 C to +125 CSO14plastic small outline package; 14 leads;body width mmSOT108-174HC21PW-40 C to +125 CTSSOP14plastic thin shrink small outline package; 14 leads;body width mmSOT402-14.

2 Functional diagram001aab9751A1B1C1D12461Y52A2B2C2D9 101282Y13 Fig. diagram001aab9731A1B1C1D12461Y52A2B2C2D9 101282Y13 Fig. symbolNexperia74HC21 Dual 4-input AND gate001aab974&61245&89101213 Fig. Logic symbol001aab976 ABCDYFig. diagram5. Pinning packageSOT108-1 (SO14) packageSOT402-1 (TSSOP14) Pin descriptionTable 2. Pin descriptionSymbolPinDescription1A, 1B, 1C, 1D1, 2, 4, 5data , 11not connected1Y6data outputGND7ground (0 V)2Y8data output2A, 2B, 2C, 2D9, 10, 12, 13data inputVCC14supply voltage74HC21 All information provided in this document is subject to legal disclaimers. Nexperia 2023. All rights reservedProduct data sheetRev. 9 2 May 20232 / 11 Nexperia74HC21 Dual 4-input AND gate6. Functional descriptionTable 3. Function tableH = HIGH voltage level; L = LOW voltage level; X = don t Limiting valuesTable 4.

3 Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).SymbolParameterConditionsMinMaxUnitVC Csupply +7 VIIK input clamping currentVI < V or VI > VCC + V[1]- 20mAIOK output clamping currentVO < V or VO > VCC + V[1]- 20mAIOoutput V < VO < VCC + V- 25mAICC supply current-50mAIGND ground current-50-mATstgstorage temperature-65+150 CPtottotal power dissipation[2]-500mW[1]The input and output voltage ratings may be exceeded if the input and output current ratings are observed.[2]For SOT108-1 (SO14) package: Ptot derates linearly with mW/K above 100 SOT402-1 (TSSOP14) package: Ptot derates linearly with mW/K above 81 Recommended operating conditionsTable 5. Recommended operating conditionsVoltages are referenced to GND (ground = 0 V)SymbolParameterConditionsMinTypMaxUnit VCCsupply voltage0-VCCVVO output voltage0-VCCVVCC = V--625ns/VVCC = t/ Vinput transition rise and fallrateVCC = V--83ns/VTambambient temperature-40-+125 C74HC21 All information provided in this document is subject to legal disclaimers.

4 Nexperia 2023. All rights reservedProduct data sheetRev. 9 2 May 20233 / 11 Nexperia74HC21 Dual 4-input AND gate9. Static characteristicsTable 6. Static characteristicsAt recommended operating conditions; voltages are referenced to GND (ground = 0 V).25 C-40 C to +85 C-40 C to +125 CSymbolParameterConditionsMinTypMaxMinMa xMinMaxUnitVCC = = voltageVCC = = = voltageVCC = = VIH or VILIO = -20 A; VCC = = -20 A; VCC = = -20 A; VCC = = mA; VCC = voltageIO = mA; VCC = = VIH or VILIO = 20 A; VCC = = 20 A; VCC = = 20 A; VCC = = mA; VCC = voltageIO = mA; VCC = leakagecurrentVI = VCC or GND; VCC = V-- 1- 1 AICC supply currentVI = VCC or GND; IO = 0 A;VCC = information provided in this document is subject to legal disclaimers. Nexperia 2023.

5 All rights reservedProduct data sheetRev. 9 2 May 20234 / 11 Nexperia74HC21 Dual 4-input AND gate10. Dynamic characteristicsTable 7. Dynamic characteristicsGND = 0 V; test circuit see Fig. C-40 C to +85 C-40 C to +125 CSymbolParameterConditionsMinTypMaxMinMa xMinMaxUnitnA, nB, nC or nD to nY;see Fig. 5[1]VCC = V-33110-140-165nsVCC = V-1222-28-33nsVCC = V-1019-24-28nstpdpropagationdelayVCC = V; CL = 15 pF-10-----nsnY output; see Fig. 5[2]VCC = V-1975-95-110nsVCC = V-715-19-22nstttransition timeVCC = V-613-16-19nsCPDpowerdissipationcapacita nceVI = GND to VCC[3]-15-----pF[1]tpd is the same as tPHL and tPLH.[2]tt is the same as tTHL and tTLH.[3]CPD is used to determine the dynamic power dissipation (PD in W):PD = CPD x VCC 2 x fi x N + (CL x VCC 2 x fo) where:fi = input frequency in MHz;fo = output frequency in MHz;CL = output load capacitance in pF;VCC = supply voltage in V;N = number of inputs switching; (CL x VCC 2 x fo) = sum of Waveforms and test circuit001aab977nA, nB, nC, nD input nY output VMVXVItPHLtTHLtTLHtPLHVOHVMVYVOLGND Measurement points are given in Table and VOH are typical voltage output levels that occur with the output showing the input (nA, nB, nC, nD) to output (nY) propagation delays and the output transitiontimes74HC21 All information provided in this document is subject to legal disclaimers.

6 Nexperia 2023. All rights reservedProduct data sheetRev. 9 2 May 20235 / 11 Nexperia74HC21 Dual 4-input AND gateTable 8. Measurement VCC001aah768 tWtWtrtrtfVMVI negative pulseGNDVI positive pulseGND10 %90 %90 %10 %VMVMVMtfVCCDUTRTVIVOCLGTest data is given in Table test circuit:RT = termination resistance should be equal to output impedance Zo of the pulse generator;CL = load capacitance including jig and probe circuit for measuring switching timesTable 9. Test dataInputLoadVItr, ns15 pF, 50 pFtPLH, tPHL74HC21 All information provided in this document is subject to legal disclaimers. Nexperia 2023. All rights reservedProduct data sheetRev. 9 2 May 20236 / 11 Nexperia74HC21 Dual 4-input AND gate11. Package outlineUNIT A max. A 1 A 2 A 3 b p c D (1) E (1) (1) e H E L L p Q Z y w v REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm inches 8 0 o o DIMENSIONS (inch dimensions are derived from the original mm dimensions) Note 1.

7 Plastic or metal protrusions of mm ( inch) maximum per side are not included. SOT108-1 X w M A A 1 A 2 b p D H E L p Q detail X E Z e c L v M A (A ) 3 A 7 8 1 14 y 076E06 MS-012 pin 1 index 99-12-27 03-02-19 0 5 mm scale SO14: plastic small outline package; 14 leads; body width mm SOT108-1 Fig. outline SOT108-1 (SO14)74HC21 All information provided in this document is subject to legal disclaimers. Nexperia 2023. All rights reservedProduct data sheetRev. 9 2 May 20237 / 11 Nexperia74HC21 Dual 4-input AND gateUNIT A 1 A 2 A 3 b p c D (1) E (2) (1) e H E L L p Q Z y w v REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 8 0 o o 1 DIMENSIONS (mm are the original dimensions) Notes 1.

8 Plastic or metal protrusions of mm maximum per side are not included. 2. Plastic interlead protrusions of mm maximum per side are not included. SOT402-1 MO-153 99-12-27 03-02-18 w M b p D Z e 1 7 14 8 A A 1 A 2 L p Q detail X L (A ) 3 H E E c v M A X A y 0 5 mm scale TSSOP14: plastic thin shrink small outline package; 14 leads; body width mm SOT402-1 A max. pin 1 index Fig. outline SOT402-1 (TSSOP14)74HC21 All information provided in this document is subject to legal disclaimers. Nexperia 2023. All rights reservedProduct data sheetRev. 9 2 May 20238 / 11 Nexperia74HC21 Dual 4-input AND gate12. AbbreviationsTable 10. AbbreviationsAcronymDescriptionCMOSC omplementary Metal Oxide SemiconductorDUTD evice Under TestESDE lectroStatic DischargeHBMH uman Body ModelMMMachine Model13. Revision historyTable 11.

9 Revision historyDocument IDRelease dateData sheet statusChange noticeSupersedes74HC21 data sheet-74HC21 : The format of this data sheet has been redesigned to comply with the identityguidelines of Nexperia . Legal texts have been adapted to the new company name where data sheet-74HC21 : Type number 74HC21DB (SOT337-1/SSOP14) removed. Section 2 data sheet-74HC21 : Type number 74HC21N (SOT27-1) data sheet-74HC21 :Section 2: Typo corrected in the specified temperature data sheet-74HC21 :Table 1: Type number 74 HCT21PW changed to data sheet-74HC21 : The format of this data sheet has been redesigned to comply with the new identityguidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Added type number 74HC21PW (TSSOP14 package).74HC21 data sheet-74HC_HCT21_CNV specification-74HC_HCT21 specification--74HC21 All information provided in this document is subject to legal disclaimers.

10 Nexperia 2023. All rights reservedProduct data sheetRev. 9 2 May 20239 / 11 Nexperia74HC21 Dual 4-input AND gate14. Legal informationData sheet statusDocument status[1][2]Productstatus [3]DefinitionObjective [short]data sheetDevelopmentThis document contains data fromthe objective specification forproduct [short]data sheetQualificationThis document contains data fromthe preliminary [short]data sheetProductionThis document contains the productspecification.[1]Please consult the most recently issued document before initiating orcompleting a design.[2]The term 'short data sheet' is explained in section "Definitions".[3]The product status of device(s) described in this document may havechanged since this document was published and may differ in case ofmultiple devices. The latest product status information is available onthe internet at The document is a draft version only.


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