Dual Pseudo Differential 16-Bit, 1 MSPS ... - Analog …

1 dual Pseudo Differential 16-Bit, 1 msps PulSAR ADC mW in QSOP Data Sheet AD7902 Rev. B Document Feedback Information furnished by Analog devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog devices . Trademarks and registered trademarks are the property of their respective owners.

2 One Technology Way, Box 9106, Norwood, MA 02062-9106, Tel: 2014 2015 Analog devices , Inc. All rights reserved. Technical Support FEATURES 16-bit resolution with no missing codes Throughput: 1 msps Low power dissipation mW at 1 msps (VDD1 and VDD2 only) mW at 1 msps (total) 140 W at 10 kSPS INL: LSB typical, LSB maximum SINAD: 91 dB at 1 kHz THD: 105 dB at 1 kHz Pseudo Differential Analog input range 0 V to VREF with VREF between V to V Allows use of any input range Easy to drive with the ADA4841-1/ADA4841-2 No pipeline delay Single-supply V operation with V/3 V/5 V logic interface Serial port interface (SPI) QSPI/MICROWIRE/DSP compatible 20-lead QSOP package Wide operating temperature range.

3 40 C to +125 C APPLICATIONS Battery-powered equipment Communications Automated test equipment (AT E) Data acquisition Medical instrumentation Redundant measurement Simultaneous sampling GENERAL DESCRIPTION The AD7902 is a dual 16-bit, successive approximation, Analog -to-digital converter (ADC) that operates from a single power supply, VDDx, per ADC. It contains two low power, high speed, 16-bit sampling ADCs and a versatile serial port interface (SPI). On the CNVx rising edge, the AD7902 samples an Analog input, IN+, in the range of 0 V to VREF with respect to a ground sense, IN.

4 The externally applied reference voltage of the REFx pins (VREF) can be set independently from the supply voltage pins, VDDx. The power of the device scales linearly with throughput. Using the SDIx inputs, the SPI-compatible serial interface can also daisy-chain multiple ADCs on a single 3-wire bus and provide an optional busy indicator. It is compatible with V, V, 3 V, or 5 V logic, using the separate VIOx supplies. The AD7902 is available in a 20-lead QSOP package with operation specified from 40 C to +125 C. Table 1. MSOP 14-/16-/18-Bit PulSAR ADCs Bits 100 kSPS 250 kSPS 400 kSPS to 500 kSPS 1000 kSPS ADC Driver 18 AD76911 AD76901 AD79821 ADA4941-1 ADA4841-1 ADA4841-2 16 AD7680 AD76851 AD76861 AD79801 ADA4941-1 AD7683 AD76871 AD76881 AD7903 ADA4841-1 AD7684 AD7694 AD76931 AD7902 ADA4841-2 14 AD7940 AD79421 AD79461 1 Pin-for-pin compatible.

5 FUNCTIONAL BLOCK DIAGRAM Figure 1. = TO 5 VADC1IN1+IN1 VIO1 SDI1 SCK1 CNV1 SDO1 VIO1/VIO2 SDI1/SDI2 SCK1/SCK2 CNV1/CNV2 SDO1 ADC2IN2+IN2 VIO2 SDI2 SCK2 CNV2 SDO2 SDO23-WIRE OR 4-WIREINTERFACE(SPI, CS, ANDCHAIN MODES)AD79020V TO VREF0V TO VREF11756-001AD7902 Data Sheet Rev. B | Page 2 of 28 TABLE OF CONTENTS Features .. 1 Applications .. 1 General Description .. 1 Functional Block Diagram .. 1 Revision History .. 2 Specifications .. 3 Timing Specifications .. 5 Absolute Maximum Ratings .. 6 ESD Caution .. 6 Pin Configuration and Function Descriptions .. 7 Typical Performance Characteristics.

6 8 Terminology .. 13 Theory of Operation .. 14 Circuit Information .. 14 Converter Operation .. 14 Typical Connection Diagram .. 15 Analog Inputs .. 15 Driver Amplifier Choice .. 16 Voltage Reference Input .. 16 Power Supply .. 17 Digital Interface .. 17 CS Mode .. 18 Chain Mode .. 22 Applications Information .. 24 Simultaneous Sampling .. 24 Functional Saftey Considerations .. 25 Layout .. 26 Evaluating Performance of the AD7902 .. 26 Outline Dimensions .. 27 Ordering Guide .. 27 REVISION HISTORY 8/15 Rev. A to Rev. B Changed ADA4841-x to ADA4841-1/ADA4841-2.

7 Throughout Change to Absolute Input Voltage Parameter, Table 2 .. 3 Changes to Voltage Reference Input Section .. 16 Updated Outline Dimensions .. 27 7/14 Rev. 0 to Rev. A Changed Standby Current Unit from nA to A .. 4 Changes to Power Supply Section .. 17 2/14 Revision 0: Initial Version Data Sheet AD7902 Rev. B | Page 3 of 28 SPECIFICATIONS VDD = V, VIO = V to V, VREF = 5 V, TA = 40 C to +125 C, unless otherwise Table 2. Parameter Test Conditions/Comments Min Typ Max Unit RESOLUTION 16 Bits Analog INPUT2 Voltage Range INx+ INx 0 VREF V Absolute Input Voltage INx+ VREF + V INx 0 + V Analog Input CMRR fIN = 450 kHz 67 dB Leakage Current at 25 C Acquisition phase 200 nA ACCURACY No Missing Codes 16 Bits Differential Nonlinearity Error3 VREF = 5 V + LSB VREF = V LSB Integral Nonlinearity Error3 VREF = 5 V + LSB VREF = V LSB Transition Noise3 VREF = 5 V LSB VREF = V LSB Gain Error4 TMIN to TMAX + % FS

8 Gain Error Temperature Drift ppm/ C Gain Error Match4 TMIN to TMAX % FS Zero Error4 TMIN to TMAX + mV Zero Temperature Drift ppm/ C Zero Error Match4 TMIN to TMAX mV Power Supply Sensitivity3 VDD = V 5% LSB THROUGHPUT Conversion Rate VIO V up to 85 C, VIO V above 85 C, up to 125 C 0 1 msps Transient Response Full-scale step 290 ns AC ACCURACY5 Dynamic Range VREF = 5 V 92 dB VREF = V 87 dB Oversampled Dynamic Range fOUT = 10 kSPS 111 dB Signal-to-Noise Ratio (SNR) fIN = 1 kHz, VREF = 5 V dB fIN = 1 kHz, VREF = V dB Spurious-Free Dynamic Range (SFDR) fIN = 1 kHz 105 dB Total Harmonic Distortion (THD) fIN = 1 kHz 105 dB Signal-to-Noise-and-Distortion Ratio (SINAD) fIN = 1 kHz, VREF = 5 V 89 91 dB fIN = 1 kHz, VREF = V 84 86 dB Channel-to-Channel Isolation fIN = 10 kHz 112 dB 1 The voltages for the VDDx, VIOx, and REFx pins are indicated by VDD, VIO, and VREF, respectively.

9 2 For information regarding input impedance, see the Analog Inputs section. 3 For the 5 V input range, 1 LSB = V. For the V input range, 1 LSB = V. 4 See the Terminology section. These specifications include full temperature range variation, but they do not include the error contribution from the external reference. 5 All specifications in decibels (dB) are referred to a full-scale input FSR. Although these parameters are referred to full scale, they are tested with an input signal at dB below full scale, unless otherwise specified. AD7902 Data Sheet Rev.

10 B | Page 4 of 28 VDD = V, VIO = V to V, TA = 40 C to +125 C, unless otherwise Table 3. Parameter Test Conditions/Comments Min Typ Max Unit REFERENCE Voltage Range V Load Current 1 msps , VREF = 5 V, each ADC 330 A SAMPLING DYNAMICS 3 dB Input Bandwidth 10 MHz Aperture Delay VDD = V ns Aperture Delay Match VDD = V ns DIGITAL INPUTS Logic Levels VIL VIO > 3 V + VIO V VIO 3 V + VVIO V VIH VIO > 3 V VIO VIO + V VIO 3 V VIO VIO + V IIL 1 +1 A IIH 1 +1 A DIGITAL OUTPUTS Data Format Straight binary Bits Pipeline Delay No delay.