LTC6820 - isoSPI Isolated Communications Interface

1 LTC68201 Rev CFor more information FeedbackTYPICAL APPLICATION FEATURESDESCRIPTIONisoSPI Isolated Communications InterfaceThe LT C 6820 provides bidirectional SPI Communications between two Isolated devices through a single twisted-pair connection. Each LTC6820 encodes logic states into signals that are transmitted across an isolation barrier to another LTC6820 . The receiving LTC6820 decodes the transmission and drives the slave bus to the appropri-ate logic states. The isolation barrier can be bridged by a simple pulse transformer to achieve hundreds of volts of LTC6820 drives differential signals using matched source and sink currents, eliminating the requirement for a transformer center tap and reducing EMI.

2 Precision window comparators in the receiver detect the differential signals. The drive currents and the comparator thresholds are set by a simple external resistor divider, allowing the system to be optimized for required cable lengths and desired signal-to-noise to SPI Slave Isolated InterfaceData Rate vs Cable LengthAPPLICATIONS nAEC-Q100 Qualified for Automotive Applications n1 Mbps Isolated SPI Data Communications nSimple Galvanic Isolation Using Standard Transformers nBidirectional Interface Over a Single Twisted Pair nSupports Cable Lengths Up to 100 Meters nVery Low EMI Susceptibility and Emissions nConfigurable for High Noise Immunity or Low Power nEngineered for ISO26262 Compliant Systems nRequires No Software Changes in Most SPI Systems nUltralow, 2 A Idle Current nAutomatic Wake-Up Detection nOperating Temperature Range.

3 40 C to 125 C to Power Supply nInterfaces to All Logic from to nAvailable in 16-Lead QFN and MSOP Packages nIndustrial Networking nBattery Monitoring Systems nRemote SensorsAll registered trademarks and trademarks are the property of their respective owners. Protected by patents, including 100 METERSTWISTED PAIRLTC6820 MSTRMOSIMISOSCKCSIMMASTER CSDOSDISCKCSIP120 6820 TA01aLTC6820 MSTRMOSIMISOSCKCSIMREMOTESLAVE ICSDISDOSCKCSCABLE LENGTH (METERS)10 DATA RATE (Mbps) ASSUMEDLTC68202 Rev CFor more information CONFIGURATIONABSOLUTE MAXIMUM RATINGSI nput Supply Voltages (VDD and VDDS) to GND ..6 VPin Voltages SCK, CS, EN .. to VDDS + (6V Max) IBIAS, SLOW, IP, IM.

4 To VDD + (6V Max) All Other Pin Voltages .. to 6 VMaximum Source/Sink Current I P, I M ..30mA MOSI, MISO, SCK, CS ..20mA(Notes 1, 2, 3)161514135678 TOP VIEW17UD PACKAGE16-LEAD (3mm 3mm) PLASTIC QFNTJMAX = 150 C, JA = C/WEXPOSED PAD (PIN 17) PCB CONNECTION TO GND IS OPTIONAL91011124321 MOSIMISOSCKCSSLOWMSTRIPIMENIBIASICMPGNDV DDSPOLPHAVDD12345678 ENMOSIMISOSCKCSVDDSPOLPHA161514131211109 IBIASICMPGNDSLOWMSTRIPIMVDDTOP VIEWMS PACKAGE16-LEAD PLASTIC MSOPTJMAX = 150 C, JA = 120 C/WORDER INFORMATIONTUBE (121PC)TAPE AND REEL (2500PC)PART MARKING*PACKAGE DESCRIPTIONMSL RATINGSPECIFIED TEMPERATURE RANGELTC6820 IUD#PBFLTC6820 IUD#TRPBFLGFM16-Lead (3mm 3mm) Plastic QFN1 40 C to 85 CLTC6820 HUD#PBFLTC6820 HUD#TRPBFLGFM16-Lead (3mm 3mm)

5 Plastic QFN1 40 C to 125 CAUTOMOTIVE PRODUCTS**TUBE (37PC)TAPE AND REEL (2500PC)PART MARKING*PACKAGE DESCRIPTIONMSL RATINGSPECIFIED TEMPERATURE RANGELTC6820 IMS#PBFLTC6820 IMS#TRPBF682016-Lead Plastic MSOP1 40 C to 85 CLTC6820 IMS#3 ZZPBFLTC6820 IMS#3 ZZTRPBF682016-Lead Plastic MSOP1 40 C to 85 CLTC6820 HMS#PBFLTC6820 HMS#TRPBF682016-Lead Plastic MSOP1 40 C to 125 CLTC6820 HMS#3 ZZPBFLTC6820 HMS#3 ZZTRPBF682016-Lead Plastic MSOP1 40 C to 125 CContact the factory for parts specified with wider operating temperature ranges.*The temperature grade is identified by a label on the shipping and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.

6 **Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These models are designated with a #3ZZ suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for these Temperature Range LTC6820I .. 40 C to 85 C LTC6820H .. 40 C to 125 CSpecified Temperature Range LTC6820I .. 40 C to 85 C LTC6820H .. 40 C to 125 CStorage Temperature Range .. 65 C to 150 CLead Temperature (Soldering, 10 sec) MSOP.

7 300 CLTC68203 Rev CFor more information CHARACTERISTICS The l denotes the specifications which apply over the full specified temperature range, otherwise specifications are at TA = 25 C. VDD = to , VDDS = to , RBIAS = 2k to 20k unless otherwise specified. All voltages are with respect to SupplyVDDO perating Supply Voltage Supply Voltage Range (Level Shifting)Affects CS, SCK, MOSI, MISO and EN Current, READY/ACTIVE States (Note 4)RBIAS = 2k (IB = 1mA) 1/tCLK = 0 MHz 1/tCLK = mARBIAS = 20k (IB = ) 1/tCLK = 0 MHz 1/tCLK = mASupply Current, IDLE StateMSTR = 0V MSTR = VDDl l2 16 3 A AIDDSIO Supply Current (Note 5)SPI Inputs and EN Pin at 0V or VDDS, SPI Outputs Unloadedl1 ABiasingVBIASV oltage on IBIAS PinREADY/ACTIVE State IDLE VIBI solated Interface Bias Current (Note 6)

8 RBIAS = 2k to 20klVBIAS/RBIASmAAIBI solated Interface Current GainVA IB = 1mA IB = l18 1820 2022 24mA/mA mA/mAVAT ransmitter Pulse AmplitudeVA = |VIP VIM| VDD < VDD lVDD VVICMPT hreshold-Setting Voltage on ICMP PinVTCMP = ATCMP (ICMP)Leakage Current on ICMP PinVICMP = 0V to VDDl 1 AILEAK(IP/IM)Leakage Current on IP and IM PinsIDLE State, VIP = VIM = 0V to VDDl 2 AATCMPR eceiver Comparator Threshold Voltage GainVCM = VDD/2 to VDD , VICMP = to Common Mode BiasIP/IM Not Driving(VDD VICMP/3 167mV)VRINR eceiver Input Resistance Single-Ended to IP or IMl263542k Idle/Wake-Up (See Figure 13, 14, 15)VWAKED ifferential Wake-Up Voltage (See Figure 13)tDWELL = 240nsl240mVtDWELLD well Time at VWAKEVWAKE = 240mVl240nstREADYS tart-Up Time After Wake Detectionl8 stIDLEIdle Time-Out I/OVIH(CFG)Digital Voltage Input High, Configuration Pins (PHA, POL, MSTR, SLOW)VDD = to (POL, PHA, MSTR, SLOW) VDDVVIL(CFG)

9 Digital Voltage Input Low, Configuration Pins (PHA, POL, MSTR, SLOW)VDD = to (POL, PHA, MSTR, SLOW) VDDVVIH(SPI)Digital Voltage Input High, SPI Pins (CS, SCK, MOSI, MISO)VDDS = to VDDS = to VDDS VDDSV VVIL(SPI)Digital Voltage Input Low, SPI Pins (CS, SCK, MOSI, MISO)VDDS = to VDDS = to VDDS VDDSV VVIH(EN)Digital Voltage Input High, EN PinVDDS = to VDDS = to l2 VDDSV VVIL(EN)Digital Voltage Input Low, EN PinVDDS = to VDDS = to VDDSV VVOHD igital Voltage Output High (CS and SCK)VDDS = , Sourcing 2mA VDDS = , Sourcing 1mAl lVDDS VDDS VVOLD igital Voltage Output Low (MOSI, MISO, CS, SCK)VDDS = , Sinking VDDS = , Sinking 1mAl VLTC68204 Rev CFor more information CHARACTERISTICS The l denotes the specifications which apply over the full specified junction temperature range, otherwise specifications are at TA = 25 C.

10 VDD = to , VDDS = to , RBIAS = 2k to 20k unless otherwise specified. All voltages are with respect to (DIG)Digital Pin Input Leakage CurrentPHA, POL, MSTR, SLOW = 0V to VDD CS, SCK, MOSI, MISO, EN = 0V to VDDSl 1 ACI/OInput/Output Pin Capacitance(Note 9)10pFIsolated Pulse Timing (See Figure 2)t1/2PW(CS)Chip-Select Half-Pulse Widthl120150180nstINV(CS)Chip-Select Pulse Inversion Delayl200nstDEL(CS)Chip-Select Response Delayl140190nst PW(D)Data Half-Pulse Widthl405060nstINV(D)Data Pulse Inversion Delayl70nstDEL(D)Data Response Delay(Note 8)l75120nsisoSPI Timing Master (See Figure 3, 4)tCLKSCK Latching Edge to SCK Latching Edge(Note 7) SLOW = 0 SLOW = 1l 5 s st1 MOSI Setup Time Before SCK Latching Edge(Note 8)l25nst2 MOSI Hold Time After SCK Latching Edgel25nst3 SCK LowtCLK = t3 + t4 sl50nst4 SCK HightCLK = t3 + t4 sl50nst5CS Rising Edge to CS Falling Edge1 MHz isoSPI Slave, tCLK > 1 s2 MHz isoSPI Slave, s < tCLK < 1 st6 SCK Latching Edge to CS Rising Edge (Note 7)1 MHz isoSPI Slave, tCLK > 1 sl1 s2 MHz isoSPI Slave, s < tCLK < 1 st7CS Falling Edge to SCK Latch Edge (Note 7)