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RM0383 Reference manual - STMicroelectronics

November 2018RM0383 Rev 31/844RM0383 Reference manualSTM32F411xC/E advanced Arm -based 32-bit MCUsIntroductionThis Reference manual targets application developers. It provides complete information on how to use the memory and the peripherals of the STM32F411xC/E is part of the family of microcontrollers with different memory sizes, packages and ordering information, mechanical and electrical device characteristics refer to the information on the Arm Cortex -M4 with FPU core, refer to the Cortex -M4 with FPU Technical Reference documentsAvailable from STMicroelectronics web site ( ).

November 2018 RM0383 Rev 3 1/844 RM0383 Reference manual STM32F411xC/E advanced Arm®-based 32-bit MCUs Introduction This Reference manual targets application developers.

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Transcription of RM0383 Reference manual - STMicroelectronics

1 November 2018RM0383 Rev 31/844RM0383 Reference manualSTM32F411xC/E advanced Arm -based 32-bit MCUsIntroductionThis Reference manual targets application developers. It provides complete information on how to use the memory and the peripherals of the STM32F411xC/E is part of the family of microcontrollers with different memory sizes, packages and ordering information, mechanical and electrical device characteristics refer to the information on the Arm Cortex -M4 with FPU core, refer to the Cortex -M4 with FPU Technical Reference documentsAvailable from STMicroelectronics web site ( ).

2 STM32F411xC/E datasheet For information on the Arm -M4 core with FPU, refer to the STM32F3 Series, STM32F4 Series, STM32L4 Series and STM32L4+ Series Cortex -M4 programming manual (PM0214). Rev 3 Contents1 Documentation conventions .. of abbreviations for registers .. availability .. 352 Memory and bus architecture .. architecture .. memory bus .. peripheral bus .. bridges (APB) .. organization .. map .. SRAM .. memory overview .. banding .. configuration .. 413 Embedded Flash memory interface .. features.

3 Flash memory in STM32F411xC/E .. interface .. between CPU clock frequency and Flash memory read time . real-time memory accelerator (ART Accelerator ) .. and program operations .. the Flash control register .. parallelism .. 50RM0383 Rev 33 .. bytes .. of user option bytes .. user option bytes .. protection (RDP) .. protections .. code readout protection (PCROP) .. programmable bytes .. interface registers .. access control register (FLASH_ACR) .. key register (FLASH_KEYR) .. option key register (FLASH_OPTKEYR).

4 Status register (FLASH_SR) .. control register (FLASH_CR) .. option control register (FLASH_OPTCR) .. interface register map .. 664 CRC calculation unit .. introduction .. main features .. functional description .. registers .. register (CRC_DR) .. data register (CRC_IDR) .. register (CRC_CR) .. register map .. 695 Power controller (PWR) .. supplies .. A/D converter supply and Reference voltage .. backup domain .. regulator .. supply supervisor .. reset (POR)/power-down reset (PDR) .. reset (BOR).

5 Voltage detector (PVD) .. 75 ContentsRM03834/844RM0383 Rev modes .. down system clocks .. clock gating .. mode .. mode .. mode .. the RTC alternate functions to wake up the device from the Stop and Standby modes .. control registers .. power control register (PWR_CR) .. power control/status register (PWR_CSR) .. register map .. 896 Reset and clock control (RCC) for STM32F411xC/E .. reset .. reset .. domain reset .. clock .. clock .. configuration .. clock .. clock .. clock (SYSCLK) selection.

6 Security system (CSS) .. clock .. clock .. capability .. clock measurement using TIM5/TIM11 .. registers .. clock control register (RCC_CR) .. PLL configuration register (RCC_PLLCFGR) .. clock configuration register (RCC_CFGR) .. clock interrupt register (RCC_CIR) .. AHB1 peripheral reset register (RCC_AHB1 RSTR) .. AHB2 peripheral reset register (RCC_AHB2 RSTR) .. 113RM0383 Rev 35 APB1 peripheral reset register for (RCC_APB1 RSTR) .. APB2 peripheral reset register (RCC_APB2 RSTR) .. AHB1 peripheral clock enable register (RCC_AHB1 ENR).

7 AHB2 peripheral clock enable register (RCC_AHB2 ENR) .. APB1 peripheral clock enable register (RCC_APB1 ENR) .. APB2 peripheral clock enable register (RCC_APB2 ENR) .. AHB1 peripheral clock enable in low power mode register (RCC_AHB1 LPENR) .. AHB2 peripheral clock enable in low power mode register (RCC_AHB2 LPENR) .. APB1 peripheral clock enable in low power mode register (RCC_APB1 LPENR) .. APB2 peripheral clock enabled in low power mode register (RCC_APB2 LPENR) .. Backup domain control register (RCC_BDCR) .. clock control & status register (RCC_CSR).

8 Spread spectrum clock generation register (RCC_SSCGR) .. PLLI2S configuration register (RCC_PLLI2 SCFGR) .. Dedicated Clocks Configuration Register (RCC_DCKCFGR) .. register map .. 1367 System configuration controller (SYSCFG) .. compensation cell .. registers .. memory remap register (SYSCFG_MEMRMP) .. peripheral mode configuration register (SYSCFG_PMC) .. external interrupt configuration register 1 (SYSCFG_EXTICR1) .. external interrupt configuration register 2 (SYSCFG_EXTICR2) .. external interrupt configuration register 3 (SYSCFG_EXTICR3).

9 External interrupt configuration register 4 (SYSCFG_EXTICR4) .. cell control register (SYSCFG_CMPCR) .. register map .. 1448 General-purpose I/Os (GPIO) .. introduction .. 145 ContentsRM03836/844RM0383 Rev main features .. functional description .. I/O (GPIO) .. pin multiplexer and mapping .. port control registers .. port data registers .. data bitwise handling .. locking mechanism .. alternate function input/output .. interrupt/wakeup lines .. configuration .. configuration .. function configuration.

10 Configuration .. the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins .. the OSC_IN/OSC_OUT pins as GPIO PH0/PH1 port pins .. of RTC functions .. registers .. port mode register (GPIOx_MODER) (x = and H) .. port output type register (GPIOx_OTYPER) (x = and H) .. port output speed register (GPIOx_OSPEEDR) (x = and H) .. port pull-up/pull-down register (GPIOx_PUPDR) (x = and H) .. port input data register (GPIOx_IDR) (x = and H) .. port output data register (GPIOx_ODR) (x = and H) .. port bit set/reset register (GPIOx_BSRR) (x = and H).


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