Transcription of SHARC+ Core Programming Reference
1 SHARC+ core Programming Reference (Includes ADSP-SC5xx and ADSP-215xx Processors)Revision , May 2021 Part Number82-100131-01 analog devices , Technology WayNorwood, MA 02062-9106 NoticesCopyright Information 2021 analog devices , Inc., ALL RIGHTS RESERVED. This document may not be reproduced in any formwithout prior, express written consent from analog devices , in the devices , Inc. reserves the right to change this product without prior notice. Information furnished by Ana-log devices is believed to be accurate and reliable. However, no responsibility is assumed by analog devices for itsuse; nor for any infringement of patents or other rights of third parties which may result from its use.
2 No license isgranted by implication or otherwise under the patent rights of analog devices , and Service Mark NoticeThe analog devices logo, Blackfin, Blackfin+, CrossCore, EngineerZone, EZ-Board, EZ-KIT Lite, EZ-KIT Mini,EZ-Extender, SHARC, SHARC+, A2B, SigmaStudio, and VisualDSP++ are registered trademarks of analog Devi-ces, other brand and product names are trademarks or service marks of their respective + core Programming ReferenceiiContentsIntroductionSHARC+ core Design Advantages .. 1 2 Architectural Overview .. 1 2 SHARC Processor .. 1 2 SHARC+ 1 3 Differences from Previous SHARC Processors .. 1 7 Development Tools.
3 1 12 Register File Registers and core Memory-Mapped 2 1 Functional Description .. 2 1 Register File Registers .. 2 1 Register Types and Classes .. 2 2 Data Registers .. 2 4 Data Register Neighbor 2 4 Complementary Data Register 2 5 Data and Complementary Data Register 2 5 Data and Complementary Data Register Access Priorities .. 2 6 Data and Complementary Data Register Swaps .. 2 6 System Register Bit Manipulation .. 2 6 Combined Data Bus Exchange 2 7PX to Data Register Transfers .. 2 8 Immediate 40-bit Data Register Load .. 2 8PX to Memory Transfers .. 2 9PX to Memory LW Transfers .. 2 9 Uncomplementary Ureg to Memory LW 2 10 core Memory Mapped Registers (CMMR).
4 2 10 Operating Modes .. 2 11 SHARC+ core Programming ReferenceiiiAlternate (Secondary) Data 2 11 Alternate (Secondary) Data Registers SIMD 2 11 Ureg/Sysreg SIMD Mode Transfers .. 2 12 Interrupt Mode Mask .. 2 12 Processing 3 1 Functional Description .. 3 1 Single Cycle 3 2 Data Forwarding in Processing 3 2 Data Format for Computation Units .. 3 3 Arithmetic Status .. 3 3 Computation Status Update Priority .. 3 3 SIMD Computation and Status 3 4 Arithmetic Logic Unit (ALU).. 3 4 Functional 3 4 ALU Instruction Types .. 3 5 Compare Accumulation Instruction .. 3 5 Fixed-to-Float Conversion Instructions .. 3 5 Fixed-to-Float Conversion Instructions with Scaling.
5 3 5 Reciprocal/Square Root Instructions .. 3 5 Divide 3 5 Clip Instruction .. 3 6 Multiprecision Instructions .. 3 6 Arithmetic 3 6 ALU Instruction Summary .. 3 6 Multiplier .. 3 9 Functional 3 10 Multiplier 3 10 Multiplier Result Register .. 3 10 Multiply Register Instruction Types .. 3 11 Clear MRx Instruction .. 3 11ivSHARC+ core Programming ReferenceRound MRx 3 11 Multi Precision Instructions .. 3 11 Saturate MRx Instruction .. 3 12 Arithmetic 3 12 Multiplier Instruction Summary .. 3 12 Barrel Shifter .. 3 14 Functional 3 15 Shifter Instruction Types .. 3 15 Shift Compute Category .. 3 15 Shift Immediate Category.
6 3 15 Bit Manipulation 3 15 Bit Field Manipulation Instructions .. 3 16 Bit Stream Manipulation Instructions .. 3 17 Floating-Point Data Pack and Unpack Instructions .. 3 19 Arithmetic 3 19 Bit FIFO Status .. 3 20 Shifter Instruction Summary .. 3 20 Multifunction 3 21 Software Pipelining for Multifunction Instructions .. 3 22 Multifunction and Data 3 22 Multifunction Input Operand Constraints .. 3 22 Multifunction Input Modifier Constraints .. 3 23 Multifunction Instruction Summary .. 3 2364-bit Instruction 3 2364-bit Data Register Coding .. 3 2564-bit Floating-Point Computation Data 3 26 Case A - 64-bit Instruction SRC Operands are DST Operands Of Previous Compute Instructions.
7 3 26 Case B - 64-bit Instruction SRC Operands are DST Operands of Previous Cond Register 3 28 Case C - 64-bit Instruction DST Operand acts as SRC Operands of the Next non-DP Compute Instruc-tion .. 3 28 Combined Data Hazards (Combinations of Cases A, B, C) .. 3 2964-bit Floating-Point Instruction Execution Cycles .. 3 30 SHARC+ core Programming Referencev64-bit Floating-Point Register Aliases in Long Word Memory 3 3564-bit Floating-Point SIMD Mode .. 3 3664-bit Floating-Point Computation Register Load Priorities .. 3 36 Operating Modes .. 3 37 ALU Saturation .. 3 37 Short Word Sign 3 37 Floating-Point Boundary Mode .. 3 37 Rounding Mode.
8 3 38 Multiplier Result Register 3 39 SIMD Mode .. 3 39 Conditional Computations in SIMD 3 40 Interrupt Mode Mask .. 3 40 Arithmetic 3 40 Arithmetic Exception Acknowledge .. 3 41 SIMD Computation Exceptions .. 3 41 Program 4 2 Functional Description .. 4 3 Instruction Pipeline .. 4 3 VISA Instruction Alignment Buffer (IAB) .. 4 5 Linear Program 4 5 Direct Addressing .. 4 6 Illegal System Accesses Conditions .. 4 6 Variation In Program 4 7 Functional Description .. 4 7 Hardware Stacks .. 4 7PC Stack Access .. 4 8PC Stack Status .. 4 8PC Stack Manipulation .. 4 9PC Stack Access Priorities .. 4 9viSHARC+ core Programming ReferenceStatus Stack Access.
9 4 9 Status Stack Status .. 4 10 Instruction Driven Branches .. 4 10 Branch 4 11 Direct Versus Indirect 4 14 Restrictions for VISA Operation .. 4 14 Delayed Branches (DB).. 4 15 Branch Listings .. 4 15 Operating Mode .. 4 20 Interrupt Branch Mode .. 4 21 Interrupt Processing Stages .. 4 21 Interrupt Categories .. 4 22 Interrupt Processing .. 4 24 Latching Interrupts .. 4 25 Interrupt 4 25 Interrupt (Pseudo) Self-Nesting .. 4 25 Self-Nesting for the System Event Controller Interrupt (SECI).. 4 26 Release from 4 28 Causes of Delayed Interrupt Processing .. 4 29 Interrupt Mask Mode .. 4 29 Interrupt Nesting Mode .. 4 30 Loop Sequencer.
10 4 32 Loop Categories .. 4 32 Counter-Based F1-Active Loop .. 4 33 Counter-Based E2-Active Loop .. 4 35 Loop Categorization into F1-Active or E2-Active .. 4 37 Arithmetic Loops .. 4 37 Indefinite Loops .. 4 39 Loop Resources .. 4 39 Loop Stack .. 4 39 Loop Address Stack Access .. 4 39 Loop Address Stack 4 40 SHARC+ core Programming ReferenceviiLoop Address Stack 4 40 Loop Counter Stack Access .. 4 40 Loop Counter Stack 4 40 Loop Counter Stack 4 41 Loop Counter Expired (If Not LCE Condition) in Counter-Based Loops .. 4 41 Restrictions on Ending 4 41 VISA-Related Restrictions on Hardware Loops .. 4 42 Nested 4 42 Example For Six Nested Loops.
