Two Selectable Inputs, 8 LVPECL Outputs ... - …

1 Two Selectable Inputs, 8 lvpecl outputs , SiGe Clock fanout BufferData sheet adclk948 Rev. B Document Feedback Information furnished by analog devices is believed to be accurate and reliable. However, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of analog devices . Trademarks and registered trademarks are the property of their respective owners. One Technology Way, Box 9106, Norwood, MA 02062-9106, : 2009 2016 analog devices , Inc. All rights reserved.

2 Technical Support FEATURES 2 Selectable differential inputs GHz operating frequency 75 fs rms broadband random jitter On-chip input terminations V power supply APPLICATIONS Low jitter clock distribution Clock and data signal restoration Level translation Wireless communications Wired communications Medical and industrial imaging ATE and high performance instrumentation GENERAL DESCRIPTION The adclk948 is an ultrafast clock fanout buffer fabricated on the analog devices , Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process. This device is designed for high speed applications requiring low jitter. The device has two Selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with center tapped, differential, 100 on-chip termination resistors.

3 The inputs accept dc-coupled LVPECL , CML, V CMOS (single-ended), and ac-coupled V CMOS, LVDS, and LVPECL inputs. A VREFx pin is available for biasing ac-coupled inputs. The adclk948 features eight full-swing emitter coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply. The output stages are designed to directly drive 800 mV each side into 50 terminated to VCC 2 V for a total differential output swing of V. The adclk948 is available in a 32-lead LFCSP and specified for operation over the standard industrial temperature range of 40 C to +85 C. FUNCTIONAL BLOCK DIAGRAM Q0Q0Q1Q1Q2Q2Q3Q3Q4Q4Q5Q5Q6Q6Q7Q7VT0 VREF0 VREF1IN_SELCLK0 CLK0VT1 CLK1 CLK1 LVPECLADCLK948 REFERENCEREFERENCE08280-001 Figure 1.

4 adclk948 data sheet Rev. B | Page 2 of 12 TABLE OF CONTENTS Features .. 1 Applications .. 1 General Description .. 1 Functional Block Diagram .. 1 Revision History .. 2 Specifications .. 3 Electrical Characteristics .. 3 Absolute Maximum Ratings .. 5 Determining Junction Temperature .. 5 ESD Caution .. 5 Thermal Performance .. 5 Pin Configuration and Function Descriptions ..6 Typical Performance Characteristics ..7 Functional Description ..9 Clock Inputs ..9 Clock Outputs ..9 Clock input Select (IN_SEL) 10 PCB Layout Considerations .. 10 input Termination Options .. 11 Outline Dimensions .. 12 Ordering Guide .. 12 REVISION HISTORY 8/2016 Rev. A to Rev. B Changed CP-32-8 to CP-32-21 .. Throughout Changes to Figure 2 and Ta b l e 7.

5 6 Updated Outline Dimensions .. 12 Changes to Ordering Guide .. 12 6/2010 Rev. 0 to Rev. A Changed output Voltage Differential Parameter to output Voltage, Single Ended Parameter, Table 1 .. 3 Changes to output Voltage, Single Ended Parameter, Table 1 .. 3 7/2009 Revision 0: Initial Version data sheet adclk948 Rev. B | Page 3 of 12 SPECIFICATIONS ELECTRICAL CHARACTERISTICS Ty pi c a l ( Typ column) values are given for VCC VEE = V and TA = 25 C, unless otherwise noted. Minimum (Min column) and maximum (Max column) values are given over the full VCC VEE = V 10% and TA = 40 C to +85 C variation, unless otherwise noted. Table 1. Clock Inputs and Outputs Parameter Symbol Min Typ Max Unit Test Conditions/Comments DC input CHARACTERISTICS input Common Mode Voltage VICM VEE + VCC V input Differential Range VID V p-p V between input pins input Capacitance CIN pF input Resistance Single-Ended Mode 50 Differential Mode 100 Common Mode 50 k Open VTx input Bias Current 20 A Hysteresis 10 mV DC output CHARACTERISTICS output Voltage High Level VOH VCC VCC V 50 to (VCC V) output Voltage Low Level VOL VCC VCC V 50 to (VCC V) output Voltage, Single Ended VO 610 960 mV VOH VOL, output static Reference Voltage VREF output Voltage (VCC + 1)

6 /2 V 500 A to +500 A output Resistance 235 Table 2. Timing Characteristics Parameter Symbol Min Typ Max Unit Test Conditions/Comments AC PERFORMANCE Maximum output Frequency GHz See Figure 4 for differential output voltage vs. frequency, > V differential output swing output Rise Time tR 40 75 90 ps 20% to 80% measured differentially output Fall Time tF 40 75 90 ps Propagation Delay tPD 175 210 245 ps VICM = 2 V, VID = V p-p Temperature Coefficient 50 fs/ C output -to- output Skew1 9 25 ps Part-to-Part Skew 45 ps VID = V p-p Additive Time Jitter Integrated Random Jitter 28 fs rms BW = 12 kHz 20 MHz, CLK = 1 GHz Broadband Random Jitter2 75 fs rms VID = V p-p, 8 V/ns, VICM = 2 V Crosstalk-Induced Jitter3 90 fs rms CLOCK output PHASE NOISE Absolute Phase Noise input slew rate > 1 V/ns (see Figure 11, the phase noise plot, for more details)

7 FIN = 1 GHz 119 dBc/Hz @100 Hz offset 134 dBc/Hz @1 kHz offset 145 dBc/Hz @10 kHz offset 150 dBc/Hz @100 kHz offset 150 dBc/Hz >1 MHz offset 1 The output skew is the difference between any two similar delay paths while operating at the same voltage and temperature. 2 Measured at the rising edge of the clock signal; calculated using the SNR of the ADC method. 3 This is the amount of added jitter measured at the output while two related, asynchronous, differential frequencies are applied to the inputs. adclk948 data sheet Rev. B | Page 4 of 12 Table 3. input Select Control Pin Parameter Symbol Min Typ Max Unit Logic 1 Voltage VIH VCC VCC V Logic 0 Voltage VIL VEE 1 V Logic 1 Current IIH 100 A Logic 0 Current IIL mA Capacitance 2 pF Table 4.

8 Power Parameter Symbol Min Typ Max Unit Test Conditions/Comments POWER SUPPLY Supply Voltage Requirement VCC VEE V V + 10% Power Supply Current Static Negative Supply Current IVEE 96 120 mA VCC VEE = V 10% Positive Supply Current IVCC 288 330 mA VCC VEE = V 10% Power Supply Rejection1 PSRVCC <3 ps/V VCC VEE = V 10% output Swing Supply Rejection2 PSRVCC 28 dB VCC VEE = V 10% 1 Change in tPD per change in VCC. 2 Change in output swing per change in VCC. data sheet adclk948 Rev. B | Page 5 of 12 ABSOLUTE MAXIMUM RATINGS Table 5. Parameter Rating Supply Voltage VCC VEE 6 V input Voltage CLK0, CLK1, CLK0, CLK1, IN_SEL VEE V to VCC + V CLK0, CLK1, CLK0, CLK1 to VTx Pin (CML, LVPECL Termination) 40 mA CLK0, CLK1 to CLK0, CLK1 V input Termination, VTx to CLK0, CLK1, CLK0, and CLK1 2 V Maximum Voltage on output Pins VCC + V Maximum output Current 35 mA Voltage Reference (VREFx) VCC to VEE Operating Temperature Range Ambient 40 C to +85 C Junction 150 C Storage Temperature Range 65 C to +150 C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product.

9 This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. DETERMINING JUNCTION TEMPERATURE To determine the junction temperature on the application printed circuit board (PCB), use the following equation: TJ = TCASE + ( JT PD) where: TJ is the junction temperature ( C). TCASE is the case temperature ( C) measured by the customer at the top center of the package. JT is from Ta b l e 6. PD is the power dissipation. Va l u e s o f JA are provided for package comparison and PCB design considerations. JA can be used for a first-order approxi-mation of TJ by the equation TJ = TA + ( JA PD) where TA is the ambient temperature ( C).

10 Va l u e s o f JB are provided in Ta b l e 6 for package comparison and PCB design considerations. ESD CAUTION THERMAL PERFORMANCE Table 6. Parameter Symbol Description Value1 Unit Junction-to-Ambient Thermal Resistance JA Still Air Per JEDEC JESD51-2 0 m/sec Air Flow C/W Moving Air JMA Per JEDEC JESD51-6 1 m/sec Air Flow C/W m/sec Air Flow C/W Junction-to-Board Thermal Resistance JB Moving Air Per JEDEC JESD51-8 1 m/sec Air Flow C/W Junction-to-Case Thermal Resistance JC Moving Air Per MIL-STD 883, Method Die-to-Heatsink C/W Junction-to-To p-of-Package Characterization Parameter JT Still Air Per JEDEC JESD51-2 0 m/sec Air Flow C/W 1 Results are from simulations.