Wide Dynamic Range, High Speed, Digitally …

1 Wide Dynamic Range, high speed , Digitally controlled VGA. Data Sheet ADL5202. FEATURES FUNCTIONAL BLOCK DIAGRAM. Dual independent, Digitally controlled VGAs SIDE A. SPI WITH FA, dB to +20 dB gain range PARALLEL WITH LATCH, UP/DN PWUPA VPOS. dB dB step size 150 differential input and output dB noise figure at maximum gain LOGIC. OIP3 > dBm at 200 MHz VINA+ VOUTA+. 0dB TO 3 dB upper frequency bandwidth of 700 MHz 150 +20dB 150 . VINA VOUTA . Multiple control interface options MODE0, Parallel 6-bit control interface (with latch) MODE1 CONTROL. Serial peripheral interface (SPI) (with fast attack) PM. CIRCUITRY. Gain up/down mode VOUTB+. Wide input Dynamic range VINB+. 150 . 0dB TO +20dB 150 . Low power mode option VINB VOUTB . Power-down control LOGIC. Single 5 V supply operation ADL5202. 40-lead, 6 mm 6 mm LFCSP package SIDE B PWUPB GND. 09387-001. APPLICATIONS SPI WITH FA, PARALLEL WITH LATCH, UP/DN. Differential ADC drivers Figure 1. high IF sampling receivers high output power IF amplification Instrumentation GENERAL DESCRIPTION.

2 The ADL5202 is a Digitally controlled , variable gain, wide band- The ADL5202 is powered on by applying the appropriate logic width amplifier that provides precise gain control, high output level to the PWUPx pins. The quiescent current of the ADL5202. IP3, and low noise figure. The excellent distortion performance is typically 160 mA in low power mode. When configured in high and high signal bandwidth make the ADL5202 an excellent gain performance mode for more demanding applications, the quiescent control device for a variety of receiver applications. The ADL5202 current is 210 mA. When powered down, the ADL5202 consumes also incorporates a low power mode option that lowers the supply less than 14 mA and offers excellent input-to-output isolation. current. The gain setting is preserved during power-down. For wide input Dynamic range applications, the ADL5202 Fabricated on an analog devices , Inc., high speed SiGe process, provides a broad dB gain range with dB resolution.

3 The the ADL5202 provides precise gain adjustment capabilities with gain is adjustable through multiple gain control interface options: good distortion performance and low phase error. The ADL5202. parallel, serial peripheral interface, and up/down. amplifier comes in a compact, thermally enhanced 40-lead, Incorporating proprietary distortion cancellation techniques, 6 mm 6 mm LFCSP package and operates over a temperature the ADL5202 achieves a better than dBm output IP3 at range of 40 C to +85 C. frequencies approaching 200 MHz for most gain settings. Rev. D Document Feedback Information furnished by analog devices is believed to be accurate and reliable. However, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, Box 9106, Norwood, MA 02062-9106, license is granted by implication or otherwise under any patent or patent rights of analog devices .

4 Tel: 2011 2017 analog devices , Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support ADL5202 Data Sheet TABLE OF CONTENTS. Features .. 1 Gain Up/Down Interface .. 16. Applications .. 1 Truth Table .. 17. Functional Block Diagram .. 1 Logic Timing .. 17. General Description .. 1 Circuit 18. Revision History .. 2 Basic Structure .. 18. 3 Applications Information .. 19. Absolute Maximum 5 Basic Connections .. 19. ESD Caution .. 5 ADC 19. Pin Configuration and Function Descriptions .. 6 Layout Considerations .. 21. Typical Performance Characteristics .. 8 Evaluation Board .. 22. Characterization and Test Circuits .. 15 Evaluation Board Control Software .. 22. Theory of Operation .. 16 Evaluation Board Schematics and Artwork .. 23. Digital Interface Overview .. 16 Evaluation Board Configuration Options .. 27. Parallel Digital Interface .. 16 Outline Dimensions .. 29. Serial Peripheral Interface (SPI).

5 16 Ordering Guide .. 29. REVISION HISTORY. 1/2017 Rev. C to Rev. D 9/2013 Rev. A to Rev. B. Change to Features Section and General Description Section .. 1 Changed Logic Pins Absolute Maximum Rating from V to Changes to Noise/Harmonic Performance Parameter, Table 1 .. 4 V to + V (not to exceed |VPOS V| at any time) ..5. 1/2015 Rev. B to Rev. C 12/2012 Rev. 0 to Rev. A. Changes to Table 1 .. 4 Changes to Layout Consideration Section .. 21. Change to Table 3 .. 6. 10/2011 Revision 0: Initial Version Rev. D | Page 2 of 29. Data Sheet ADL5202. SPECIFICATIONS. VS = 5 V, TA = 25 C, RS = RL = 150 at 100 MHz, high performance mode, 2 V p-p differential output, unless otherwise noted. Table 1. Parameter Test Conditions/Comments Min Typ Max Unit Dynamic PERFORMANCE. 3 dB Bandwidth VOUT < 2 V p-p ( dBm) 700 MHz Slew Rate V/ns Input Return Loss (S11) 100 MHz dB. Output Return Loss (S22) 100 MHz dB. INPUT STAGE VINA+, VINB+ and VINA , VINB pins Maximum Input Swing (Differential) Gain code = 111111 V p-p Differential Input Resistance 150.

6 Common-Mode Input Voltage V. CMRR Gain code = 000000 40 dB. GAIN. Maximum Voltage Gain Gain code = 000000 20 dB. Minimum Voltage Gain Gain code = 111111 dB. Gain Step Size dB. Gain Flatness 30 MHz < fC < 200 MHz dB. Gain Temperature Sensitivity Gain code = 000000 dB/ C. Gain Step Response For VIN = V, gain code = 111111 to 000000 15 ns Gain Conformance Error Over 10 dB gain range dB. Phase Conformance Error Over 10 dB gain range Degrees OUTPUT STAGE VOUTx+ and VOUTx pins Output Voltage Swing At P1dB, gain code = 000000 10 V p-p Differential Output Resistance Differential 150 . NOISE/HARMONIC PERFORMANCE. 46 MHz Gain code = 000000, high performance mode Second Harmonic VOUT = 2 V p-p 92 dBc Third Harmonic VOUT = 2 V p-p 105 dBc Output IP3 VOUT = 2 V p-p composite dBm 70 MHz Gain code = 000000, high performance mode Second Harmonic VOUT = 2 V p-p 96 dBc Third Harmonic VOUT = 2 V p-p 105 dBc Output IP3 VOUT = 2 V p-p composite dBm 140 MHz Gain code = 000000, high performance mode Noise Figure dB.

7 Second Harmonic VOUT = 2 V p-p 86 dBc Third Harmonic VOUT = 2 V p-p 105 dBc Output IP3 VOUT = 2 V p-p composite dBm Output 1 dB Compression Point dBm 300 MHz Gain code = 000000, high performance mode Second Harmonic VOUT = 2 V p-p 77 dBc Third Harmonic VOUT = 2 V p-p 91 dBc Output IP3 VOUT = 2 V p-p composite 45 dBm Rev. D | Page 3 of 29. ADL5202 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit POWER-UP INTERFACE PWUPA, PWUPB pins Power-Up Threshold Minimum voltage to enable the device V. Maximum voltage to enable the device V. PWUPx Input Bias Current 1 A. GAIN CONTROL INTERFACE. VIH Minimum/Maximum voltage for a logic high V. VIL Maximum voltage for a logic low Maximum Input Bias Current 1 A. SPI TIMING LATCHA and LATCHB, SCLK, SDIO, data pins fSCLK 1/tSCLK 20 MHz tDH Data hold time 5 ns tDS Data setup time 5 ns tPW SCLK high pulse width 5 ns POWER INTERFACE. Supply Voltage V. Quiescent Current, Both Channels high performance mode 210 mA. TA = 85 C 250 mA.

8 Low power mode 160 mA. TA = 85 C 180 mA. Power-Down Current, Both Channels PWUPx low 14 mA. 1. The minimum value for a logic high on the PM pin is V. Timing Diagrams tSCLK tPW. SCLK. tDH. tDS. ___ ___. CSA, CSB. tDS tDH. 09387-002. SDIO DNC DNC DNC DNC DNC DNC DNC R/W FA1 FA0 D5 D4 D3 D2 D1 D0. Figure 2. SPI Interface Read/Write Mode Timing Diagram tDS tDS. UPDN_DAT tPW. UPDN_CLK. UP DN RESET. 09387-103. tDS tDH. Figure 3. Up/Down Mode Timing Diagram LATCHA, LATCHB. A5 TO A0. 09387-104. B5 TO B0. tDH. Figure 4. Parallel Mode Timing Diagram Rev. D | Page 4 of 29. Data Sheet ADL5202. ABSOLUTE MAXIMUM RATINGS. Table 2. Stresses at or above those listed under Absolute Maximum Parameter Rating Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these Supply Voltage, VPOS or any other conditions above those indicated in the operational PWUPA, PWUPB, A0 to A5, B0 to B5, V to + V. MODE0, MODE1, PM, LATCHA, LATCHB (not to exceed |VPOS section of this specification is not implied.)

9 Operation beyond V| at any time) the maximum operating conditions for extended periods may Input Voltage, VIN+ ,VIN + V to V affect product reliability. Internal Power Dissipation W. JA (Exposed Paddle Soldered Down) C/W. JC (At Exposed Paddle) C/W. ESD CAUTION. Maximum Junction Temperature 140 C. Operating Temperature Range 40 C to +85 C. Storage Temperature Range 65 C to +150 C. Lead Temperature (Soldering, 60 sec) 240 C. Rev. D | Page 5 of 29. ADL5202 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. UPDN_DAT_A/A0. UPDN_CLK_A/A1. FA_A/A2. LATCHA. VOUTA+. VOUTA . PWUPA. VINA+. VINA . GND. 32. 31. 40. 39. 38. 37. 36. 35. 34. 33. PIN 1. CSA/A3 1 INDICATOR. 30 VOUTA . A4 2 29 VOUTA+. A5 3 28 VPOS. MODE1 4 ADL5202 27 VPOS. MODE0 5 TOP VIEW 26 VPOS. PM 6 (Not to Scale) 25 VPOS. GND 7 24 VPOS. SIDO/B5 8 EXPOSED 23 VPOS. SCLK/B4 9 PADDLE 22 VOUTB+. GS1/CSB/B3 10 21 VOUTB . 12. 13. 14. 15. 16. 17. 18. 19. 20. 11 GS0/FA_B/B2. UPDN_CLK_B/B1. UPDN_DAT_B/B0. PWUPB. GND.

10 LATCHB. VINB . VINB+. VOUTB . VOUTB+. NOTES. 09387-003. 1. THE EXPOSED PADDLE (EP) MUST BE CONNECTED TO. A LOW IMPEDANCE GROUND PAD. Figure 5. Pin Configuration Table 3. Pin Function Descriptions Pin No. Mnemonic Description 1 CSA/A3 Channel A Select (CSA). When serial mode is enabled, a logic low (0 V CSA V) selects Channel A. Bit 3 for Channel A Parallel Gain Control Interface (A3). 2 A4 Bit 4 for Channel A Parallel Gain Control Interface. 3 A5 Bit 5 (MSB) for Channel A Parallel Gain Control Interface. 4 MODE1 MSB for Mode Control. With the MODE0 pin, selects parallel, SPI, or up/down interface mode. 5 MODE0 LSB for Mode Control. With the MODE1 pin, selects parallel, SPI, or up/down interface mode. 6 PM Performance Mode. A logic low (0 V PM V) enables high performance mode. A logic high ( V PM V) enables low power mode. 7, 18, 33, EP GND Ground. The exposed paddle (EP) must be connected to a low impedance ground pad. 8 SDIO/B5 Serial Data Input/Output (SDIO). When CSA or CSB is pulled low, SDIO is used for reading and writing to the SPI port.