MC74HC74A - Dual D Flip-Flop with Set and Reset

1 Semiconductor Components Industries, LLC, 2014 August, 2014 Rev. 141 Publication Order Number: MC74HC74A /DMC74HC74 ADual D Flip-Flop with Setand ResetHigh Performance Silicon Gate CMOSThe MC74HC74A is identical in pinout to the LS74. The deviceinputs are compatible with standard CMOS outputs; with pullupresistors, they are compatible with LSTTL device consists of two D flip flops with individual Set, Reset ,and Clock inputs. Information at a D input is transferred to thecorresponding Q output on the next positive going edge of the clockinput. Both Q and Q outputs are available from each flip flop.

2 The Setand Reset inputs are Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: to V Low Input Current: mA High Noise Immunity Characteristic of CMOS Devices In Compliance with the JEDEC Standard No. A Requirements Chip Complexity: 128 FETs or 32 Equivalent Gates NLV Prefix for Automotive and Other Applications RequiringUnique Site and Control Change Requirements; AEC Q100 Qualified and PPAP Capable These Devices are Pb Free, Halogen Free and are RoHS CompliantRESET 1 DATA 1 CLOCK 1 SET 1 Reset 2 DATA 2 CLOCK 2 SET 21234131211105698Q1Q1Q2Q2 PIN 14 = VCC PIN 7 = GNDLOGIC detailed ordering and shipping information in the packagedimensions section on page 4 of this data INFORMATIONMARKING DIAGRAMSA= Assembly LocationL, WL= Wafer LotY, YY= YearW, WW= Work WeekG or G= Pb Free PackageTSSOP 14DT SUFFIXCASE 948 GSOIC 14 NBD SUFFIXCASE 751 AHC74 AGAWLYWW114HC74 AALYWGG114(Note.)

3 Microdot may be in either location)TSSOP 14 SOIC 14 NBPIN ASSIGNMENTSET 1 CLOCK 1 DATA 1 Reset 11112131489105432176 SET 2 CLOCK 2 DATA 2 Reset 2 VCCQ2Q2 GNDQ1Q1MC74HC74 TABLEI nputsOutputsSet Reset Clock DataQQLH XX HLHL XX LHLLXXH*H*HHH H LHHL LHHHLXNo ChangeHHHXNo ChangeHHXNo Change*Both outputs will remain high as long as Setand Reset are low, but the output states areunpredictable if Set and Reset go RATINGSS ymbolParameterValueUnitVCCDC Supply Voltage (Referenced to GND) to + Input Voltage (Referenced to GND) to VCC + Output Voltage (Referenced to GND) to VCC + Input Current, per Pin 20mAIoutDC Output Current, per Pin 25mAICCDC Supply Current, VCC and GND Pins 50mAPDP ower Dissipation in Still Air,SOIC Package TSSOP Package 500450mWTstgStorage Temperature 65 to +150_CTLLead Temperature, 1 mm from Case for 10 Seconds(SOIC or TSSOP Package)260300_CStresses exceeding those listed in the Maximum Ratings table may damage the device.

4 If any ofthese limits are exceeded, device functionality should not be assumed, damage may occur andreliability may be affected. Derating: SOIC Package: 7 mW/_C from 65_ to 125_CTSSOP Package: mW/_C from 65_ to 125_CRECOMMENDED OPERATING CONDITIONSS ymbolParameterMinMaxUnitVCCDC Supply Voltage (Referenced to GND) , VoutDC Input Voltage, Output Voltage (Referenced to GND)0 VCCVTAO perating Temperature, All Package Types 55+125_Ctr, tfInput Rise and Fall TimeVCC = V(Figures 1, 2, 3)VCC = VVCC = VVCC = V00001000600500400nsFunctional operation above the stresses listed in the Recommended Operating Ranges is not implied.

5 Extended exposure to stresses beyondthe Recommended Operating Ranges limits may affect device device contains protectioncircuitry to guard against damagedue to high static voltages or electricfields. However, precautions mustbe taken to avoid applications of anyvoltage higher than maximum ratedvoltages to this high impedance cir-cuit. For proper operation, Vin andVout should be constrained to therange GND v (Vin or Vout) v inputs must always betied to an appropriate logic voltagelevel ( , either GND or VCC).Unused outputs must be left ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)SymbolParameterTest ConditionsVCCVG uaranteed LimitUnit 55 to25_Cv 85_Cv 125_CVIHM inimum High Level InputVoltageVout = V or VCC V|Iout| v 20 Low Level InputVoltageVout = V or VCC V|Iout| v 20 High Level OutputVoltageVin = VIH or VIL|Iout| v 20 = VIH or VIL|Iout| v mA|Iout| v mA|Iout| v Low Level OutputVoltageVin = VIH or VIL|Iout| v 20 = VIH or VIL|Iout| v mA|Iout| v mA|Iout| v Input Leakage CurrentVin = VCC or Quiescent SupplyCurrent (per Package)

6 Vin = VCC or GNDIout = 0 ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = ns)SymbolParameterVCCVG uaranteed LimitUnit 55 to25_Cv 85_Cv 125_CfmaxMaximum Clock Frequency (50% Duty Cycle)(Figures 1 and 4) ,tPHLM aximum Propagation Delay, Clock to Q or Q(Figures 1 and 4) ,tPHLM aximum Propagation Delay, Set or Reset to Q or Q(Figures 2 and 4) ,tTHLM aximum Output Transition Time, Any Output(Figures 1 and 4) Input Capacitance 101010pFCPDP ower Dissipation Capacitance (Per Flip Flop)*Typical @ 25 C, VCC = VpF32* Used to determine the no load dynamic power consumption: PD = CPD VCC2f + ICC REQUIREMENTS (Input tr = tf = ns)SymbolParameterVCCVG uaranteed LimitUnit 55 to25_Cv 85_Cv 125_CtsuMinimum Setup Time, Data to Clock(Figure 3) Hold Time, Clock to Data(Figure 3) Recovery Time, Set or Reset Inactive to Clock(Figure 2) Pulse Width, Clock(Figure 1) Pulse Width, Set or Reset (Figure 2) , tfMaximum Input Rise and Fall Times(Figures 1, 2, 3) INFORMATIOND evicePackageShipping MC74HC74 ADGSOIC 14 NB(Pb Free)55 Units / RailNLV74HC74 ADG*SOIC 14 NB(Pb Free)55 Units / RailMC74HC74 ADR2 GSOIC 14 NB(Pb Free)2500 / Tape & ReelNLV74HC74 ADR2G*SOIC 14 NB(Pb Free)

7 2500 / Tape & ReelMC74HC74 ADTR2 GTSSOP 14(Pb Free)2500 / Tape & ReelNLV74HC74 ADTR2G*TSSOP 14(Pb Free)2500 / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q100 Qualified and WAVEFORMSF igure 1. 50%50%50%50%VCCVCCGNDGNDSET ORRESETQ OR QQ OR QCLOCKtPLHtPHL50%DATACLOCKVCCVCCGNDF igure 2. VALIDGND tsuthtrectwSETDATARESET4, 102, 121, 13 CLOCK3, 115, 96, 8QQ*Includes all probe and jig capacitanceCL*TEST POINTDEVICEUNDERTESTOUTPUTF igure 3.

8 1/fmaxCLOCKQ or QtftrVCCGND90%50%10%90%50%10%tPLHtPHLtTL HtTHLtw50%Figure 4. Figure 5. EXPANDED LOGIC DIAGRAMSOIC 14 NBCASE 751A 03 ISSUE LDATE 03 FEB 2016 SCALE 1:1114 GENERICMARKING DIAGRAM*XXXXXXXXXGAWLYWW114 XXXXX = Specific Device CodeA= Assembly LocationWL= Wafer LotY= YearWW= Work WeekG= Pb Free PackageSTYLES ON PAGE 2 NOTES:1. DIMENSIONING AND TOLERANCING PERASME , CONTROLLING DIMENSION: DIMENSION b DOES NOT INCLUDE DAMBARPROTRUSION. ALLOWABLE PROTRUSIONSHALL BE TOTAL IN EXCESS OF ATMAXIMUM MATERIAL DIMENSIONS D AND E DO NOT INCLUDEMOLD MAXIMUM MOLD PROTRUSION ALA3 DETAIL 7 0 7 : MILLIMETERS1 PITCHSOLDERING FOOTPRINT**For additional information on our Pb Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, *This information is generic.

9 Please refer todevice data sheet for actual part Free indicator, G or microdot G , mayor may not be present. Some products maynot follow the Generic CASE OUTLINEPACKAGE DIMENSIONS98 ASB42565 BDOCUMENT NUMBER:DESCRIPTION:Electronic versions are uncontrolled except when accessed directly from the Document versions are uncontrolled except when stamped CONTROLLED COPY in 1 OF 2 SOIC 14 NBonsemi and are trademarks of Semiconductor Components Industries, LLC dba onsemi or its subsidiaries in the United States and/or other countries. onsemi reservesthe right to make changes without further notice to any products herein.

10 Onsemi makes no warranty, representation or guarantee regarding the suitability of its products for any particularpurpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitationspecial, consequential or incidental damages. onsemi does not convey any license under its patent rights nor the rights of others. Semiconductor Components Industries, LLC, 14 CASE 751A 03 ISSUE LDATE 03 FEB 2016 STYLE 7:PIN 1. ANODE/CATHODE2. COMMON ANODE3. COMMON CATHODE4. ANODE/CATHODE5. ANODE/CATHODE6.