KAI-08050 - 3296 (H) x 2472 (V) Interline CCD …

1 Semiconductor Components Industries, LLC, 2016 September, 2016 Rev. 81 Publication Order Number: kai 08050 /DKAI-080503296 (H) x 2472 (V) Interline CCD Image SensorDescriptionThe kai 08050 Image Sensor is an 8 megapixel CCD in a 4/3 optical format. Based on the TRUESENSE micron InterlineTransfer CCD Platform, the sensor features broad dynamic range,excellent imaging performance, and a flexible readout architecturethat enables use of 1, 2, or 4 outputs. The sensor supports fullresolution readout up to 16 frames per second, while a Region ofInterest (ROI) mode supports partial readout of the sensor at evenhigher frame rates. A vertical overflow drain structure suppressesimage blooming and enables electronic shuttering for precise sensor shares common pin out and electrical configurationswith other devices based on the TRUESENSE micron InterlineTransfer Platform, allowing a single camera design to support multiplemembers of this sensor 1.

2 GENERAL SPECIFICATIONSP arameterTypical ValueArchitectureInterline CCD; Progressive ScanTotal Number of Pixels3364 (H) x 2520 (V)Number of Effective Pixels3320 (H) x 2496 (V)Number of Active Pixels3296 (H) x 2472 (V)Pixel mm (H) x mm (V)Active Image mm (H) x mm (V) mm (diag), 4/3 optical formatAspect Ratio4:3 Number of Outputs1, 2, or 4 Charge Capacity20,000 electronsOutput Sensitivity34 mV/e Quantum EfficiencyMono ( ABA)Gen 2 Bayer: R, G, B ( FBA)*Gen 1 Bayer: R, G, B ( CBA)46%30%, 37%, 39%29%, 37%, 39%Read Noise (f = 40 MHz)12 electrons rmsDark CurrentPhotodiodeVCCD7 electrons/s100 electrons/sDark Current Doubling C9 CDynamic Range64 dBCharge Transfer Suppression> 300 XSmear 100 dBImage Lag< 10 electronsMaximum Pixel Clock Speed40 MHzMaximum Frame RatesQuad OutputDual OutputSingle Output16 fps8 fps4 fpsPackage68 pin PGAC over GlassAR coated, 2 SidesNOTE: All parameters are specified at T = 40 C unless otherwise noted.

3 * 1. kai 08050 CCD Image SensorFeatures Bayer Color Pattern Configuration Progressive Scan Readout Flexible Readout Architecture High Frame Rate High Sensitivity Low Noise Architecture Excellent Smear Performance Package Pin Reserved for DeviceIdentificationApplications Industrial Imaging Medical Imaging SecuritySee detailed ordering and shipping information on page 2 ofthis data INFORMATIONKAI INFORMATIONT able 2. ORDERING INFORMATIONPart NumberDescriptionMarking CodeKAI 08050 ABA JD BAMonochrome, Telecentric Microlens, PGA Package,Sealed Clear Cover Glass with AR coating (both sides), Standard GradeKAI 08050 ABAS erial NumberKAI 08050 ABA JD AEMonochrome, Telecentric Microlens, PGA Package,Sealed Clear Cover Glass with AR coating (both sides), Engineering GradeKAI 08050 FBA JD BAGen2 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass with AR coating(both sides), Standard GradeKAI 08050 FBAS erial NumberKAI 08050 FBA JD AEGen2 Color (Bayer RGB), Telecentric Microlens, PGA Package, Sealed Clear Cover Glass with AR coating(both sides), Engineering GradeSee the ON Semiconductor Device Nomenclature document (TND310/D) for a full description of the naming conventionused for image sensors.

4 For reference documentation, including information on evaluation kits, please visit our web site DESCRIPTIONA rchitectureFigure 2. Block DiagramHLOD12 Dark12V1B12 Buffer1212221 Dummy1 Dummy3296H x mm x mm Pixels1648164816481648(Last VCCD Phase = V1 H1S)V2BV3BV4BV1TV2TV3TV4TH1 SaH1 BaH2 SaH2 BaRDaRaVDDaVOUTaGNDH1 SbH1 BbH2 SbH2 BbRDcRcVDDcVOUTcGNDRDdRdVDDdVOUTdGNDRDbR bVDDbVOUTbGNDV1BV2BV3BV4BV1TV2TV3TV4TH1 SdH1 BdH2 SdH2 BdH1 ScH1 BcH2 ScH2 BcH2 SLaOGaH2 SLcOGcH2 SLdOGdH2 SLbOGbESDESDSUBSUB822 10 11282210112822101128221222 12 DevIDHLOD10 1 Dark Reference PixelsThere are 12 dark reference rows at the top and 12 darkrows at the bottom of the image sensor. The dark rows are notentirely dark and so should not be used for a dark referencelevel. Use the 22 dark columns on the left or right side of theimage sensor as a dark normal circumstances use only the center 20columns of the 22 column dark reference due to potentiallight PixelsWithin each horizontal shift register there are 11 leadingadditional shift phases.

5 These pixels are designated asdummy pixels and should not be used to determine a darkreference addition, there is one dummy row of pixels at the topand bottom of the Buffer Pixels12 unshielded pixels adjacent to any leading or trailingdark reference regions are classified as active buffer pixels are light sensitive but are not tested for defectsand non AcquisitionAn electronic representation of an image is formed whenincident photons falling on the sensor plane createelectron hole pairs within the individual siliconphotodiodes. These photoelectrons are collected locally bythe formation of potential wells at each photosite. Belowphotodiode saturation, the number of photoelectronscollected at each pixel is linearly dependent upon light leveland exposure time and non linearly dependent onwavelength. When the photodiodes charge capacity isreached, excess electrons are discharged into the substrate toprevent ProtectionAdherence to the power up and power down sequence iscritical.

6 Failure to follow the proper power up andpower down sequences may cause damage to the Power Up and Power Down Sequence Color Filter PatternFigure 3. Bayer Color Filter PatternHLOD12 Dark12V1B12 Buffer1212B GGR221 Dummy1 Dummy3296H x mm x mm Pixels1648164816481648(Last VCCD Phase = V1 H1S)V2BV3BV4BV1TV2TV3TV4TH1 SaH1 BaH2 SaH2 BaRDaRaVDDaVOUTaGNDH1 SbH1 BbH2 SbH2 BbRDcRcVDDcVOUTcGNDRDdRdVDDdVOUTdGNDRDbR bVDDbVOUTbGNDV1BV2BV3BV4BV1TV2TV3TV4TH1 SdH1 BdH2 SdH2 BdH1 ScH1 BcH2 ScH2 BcH2 SLaOGaH2 SLcOGcH2 SLdOGdH2 SLbOGbESDESDSUBSUB822 10 1128221011282210112822 10 11222 12 DevIDHLODB GGRB GGRB GGRKAI DESCRIPTIONPin Description and Device OrientationFigure 4. Package Pin Designations Top ViewPixel(1,1)13456789101112131415161718 19202122V3BV1BV4 BVDDaV2 BGNDVOUTaRaRDaH2 SLaOGaH1 BbH2 BbH2 SbH1 SbN/CSUBH2 SaH1 SaH1 BaH2Ba2324H2 SLbOGb2526272829303132V1BV4 BVDDbV2 BGNDVOUTbRbRDb3334V3 BESD686665646362616059585756555453525150 494847 ESDV4TV1TV2 TVDDcVOUTcGNDRDcRcOGcH2 SLcH2 BdH1 BdH1 SdH2 SdSUBN/CH1 ScH2 ScH2 BcH1Bc4645 OGdH2 SLd4443424140393837V4TV1TV2 TVDDdVOUTdGNDRDdRd3635 DevIDV3T67V3 TKAI 3.

7 PIN DESCRIPTIONPinNameDescription1V3 BVertical CCD Clock, Phase 3, Bottom3V1 BVertical CCD Clock, Phase 1, Bottom4V4 BVertical CCD Clock, Phase 4, Bottom5 VDDaOutput Amplifier Supply, Quadrant a6V2 BVertical CCD Clock, Phase 2, Bottom7 GNDG round8 VOUTaVideo Output, Quadrant a9 RaReset Gate, Quadrant a10 RDaReset Drain, Quadrant a11H2 SLaHorizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant a12 OGaOutput Gate, Quadrant a13H1 BaHorizontal CCD Clock, Phase 1, Barrier,Quadrant a14H2 BaHorizontal CCD Clock, Phase 2, Barrier,Quadrant a15H2 SaHorizontal CCD Clock, Phase 2, Storage, Quadrant a16H1 SaHorizontal CCD Clock, Phase 1, Storage, Quadrant a17N/CNo Connect18 SUBS ubstrate19H2 SbHorizontal CCD Clock, Phase 2, Storage, Quadrant b20H1 SbHorizontal CCD Clock, Phase 1, Storage, Quadrant b21H1 BbHorizontal CCD Clock, Phase 1, Barrier,Quadrant b22H2 BbHorizontal CCD Clock, Phase 2, Barrier,Quadrant b23H2 SLbHorizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant b24 OGbOutput Gate, Quadrant b25 RbReset Gate, Quadrant b26 RDbReset Drain, Quadrant b27 GNDG round28 VOUTbVideo Output, Quadrant b29 VDDbOutput Amplifier Supply, Quadrant b30V2 BVertical CCD Clock, Phase 2, Bottom31V1 BVertical CCD Clock, Phase 1, Bottom32V4 BVertical CCD Clock, Phase 4, Bottom33V3 BVertical CCD Clock, Phase 3, Bottom34 ESDESD Protection DisablePinNameDescription68 ESDESD Protection Disable67V3 TVertical CCD Clock, Phase 3, Top66V4 TVertical CCD Clock, Phase 4, Top65V1 TVertical CCD Clock, Phase 1, Top64V2 TVertical CCD Clock, Phase 2, Top63 VDDcOutput Amplifier Supply, Quadrant c62 VOUTcVideo Output, Quadrant c61 GNDG round60 RDcReset Drain, Quadrant c59 RcReset Gate, Quadrant c58 OGcOutput Gate.

8 Quadrant c57H2 SLcHorizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant c56H2 BcHorizontal CCD Clock, Phase 2, Barrier,Quadrant c55H1 BcHorizontal CCD Clock, Phase 1, Barrier,Quadrant c54H1 ScHorizontal CCD Clock, Phase 1, Storage, Quadrant c53H2 ScHorizontal CCD Clock, Phase 2, Storage, Quadrant c52 SUBS ubstrate51N/CNo Connect50H1 SdHorizontal CCD Clock, Phase 1, Storage, Quadrant d49H2 SdHorizontal CCD Clock, Phase 2, Storage, Quadrant d48H2 BdHorizontal CCD Clock, Phase 2, Barrier,Quadrant d47H1 BdHorizontal CCD Clock, Phase 1, Barrier,Quadrant d46 OGdOutput Gate, Quadrant d45H2 SLdHorizontal CCD Clock, Phase 2, Storage, Last Phase, Quadrant d44 RDdReset Drain, Quadrant d43 RdReset Gate, Quadrant d42 VOUTdVideo Output, Quadrant d41 GNDG round40V2 TVertical CCD Clock, Phase 2, Top39 VDDdOutput Amplifier Supply, Quadrant d38V4 TVertical CCD Clock, Phase 4, Top37V1 TVertical CCD Clock, Phase 1, Top36 DevIDDevice Identification35V3 TVertical CCD Clock, Phase 3, Top1.

9 Liked named pins are internally connected and should have acommon drive N/C pins (17, 51) should be left PERFORMANCET able 4. TYPICAL OPERATION CONDITIONSU nless otherwise noted, the Imaging Performance Specifications are measured using the following SourceContinuous red, green and blue LED illuminationFor monochrome sensor, onlygreen LED operating voltages and timingTable 5. SPECIFICATIONSAll At(5C)NotesDark Field Global Non UniformityDSNU 2mVppDie27, 40 Bright Field Global Non Uniformity 25%rmsDie27, 401 Bright Field Global Peak to PeakNon UniformityPRNU 515%ppDie27, 401 Bright Field Center Non Uniformity 12%rmsDie27, 401 Maximum Photoresponse Nonlin-earityNL 2 %Design2 Maximum Gain Difference BetweenOutputsDG 10 %Design2 Maximum Signal Error due to Nonlinearity DifferencesDNL 1 %Design2 Horizontal CCD Charge CapacityHNe 55 ke DesignVertical CCD Charge CapacityVNe 40 ke DesignPhotodiode Charge CapacityPNe 20 ke Die27, 403 Horizontal CCD Charge DieVertical CCD Charge Transfer DiePhotodiode Dark CurrentIpd 770e/p/sDie40 Vertical CCD Dark CurrentIvd 100300e/p/sDie40 Image LagLag 10e DesignAntiblooming FactorXab300 DesignVertical SmearSmr 100 dBDesignRead Noisene T 12 e rmsDesign4 Dynamic RangeDR 64 dBDesign4, 5 Output Amplifier DC OffsetVodc VDie27.

10 40 Output Amplifier Bandwidthf 3db 250 MHzDie6 Output Amplifier ImpedanceROUT 127 WDie27, 40 Output Amplifier SensitivityDV/DN 34 mV/e Design1. Per color2. Value is over the range of 10% to 90% of photodiode The operating value of the substrate voltage, VAB, will be marked on the shipping container for each device. The value of VAB is set suchthat the photodiode charge capacity is 680 At 40 MHz5. Uses 20 LOG (PNe/ ne T)6. Assumes 5 pF 6. kai 08050 ABA CONFIGURATIONS WITH MAR At(5C)NotesPeak Quantum EfficiencyQEmax 46 %DesignPeak Quantum Efficiency WavelengthlQE 480 nmDesignTable 7. kai 08050 FBA GEN2 COLOR CONFIGURATIONS WITH MAR At(5C)NotesPeak Quantum EfficiencyBlueGreenRedQEmax 393730 %DesignPeak Quantum EfficiencyWavelengthBlueGreenRedlQE 460530605 nmDesignKAI PERFORMANCE CURVESQ uantum EfficiencyMonochromeFigure 5. kai 08050 ABA, Monochrome Configuration Quantum EfficiencyKAI Color (Bayer RGB) Quantum Efficiency with Microlens (Gen2 CFA vs.)