NCP51820 - High Speed Half-Bridge Driver for GaN Power ...

1 DATA Semiconductor Components Industries, LLC, 2019 August, 2021 Rev. 51 Publication Order Number: NCP51820 /DHigh Speed Half-BridgeDriver for GaN PowerSwitchesNCP51820 The NCP51820 high Speed , gate Driver is designed to meet thestringent requirements of driving enhancement mode (e mode), highelectron mobility transistor (HEMT) and gate injection transistor(GIT), gallium nitrade (GaN) Power switches in off line, half bridgepower topologies. The NCP51820 offers short and matchedpropagation delays with advanced level shift technology providing V to +650 V (typical) common mode voltage range for thehigh side drive and V to + V common mode voltage range forthe low side drive. In addition, the device provides stable dV/dtoperation rated up to 200 V/ns for both Driver output stages in highspeed switching fully protect the gate of the GaN Power transistor againstexcessive voltage stress, both drive stages employ a dedicated voltageregulator to accurately maintain the gate source drive signalamplitude.

2 The circuit actively regulates the Driver s bias rails and thusprotects against potential gate source over voltage under variousoperating NCP51820 offers important protection functions such asindependent under voltage lockout (UVLO), monitoring VDD biasvoltage and VDDH and VDDL Driver bias and thermal shutdownbased on die junction temperature of the device. Programmabledead time control can be configured to prevent cross 650 V, Integrated High Side and Low Side Gate Drivers UVLO Protections for VDD High and Low Side Drivers Dual TTL Compatible Schmitt Trigger Inputs Split Output Allows Independent Turn ON/Turn OFF Adjustment Source Capability: 1 A; Sink Capability: 2 A Separated HO and LO Driver Output Stages 1 ns Rise and Fall Times Optimized for GaN Devices SW and PGND.

3 Negative Voltage Transient up to V 200 V/ns dV/dt Rating for all SW and PGND Referenced Circuitry Maximum Propagation Delay of Less Than 50 ns Matched Propagation Delays to Less Than 5 ns User Programmable Dead Time Control Thermal Shutdown (TSD)Typical Applications Driving GaN Power Transistors used in Full or Half Bridge, LLC,Active Clamp Flyback or Forward, Totem Pole PFC andSynchronous Rectifier Topologies Industrial Inverters and Motor Drives AC to DC ConvertersQFN15 4x4, 485 FNMARKING DIAGRAMPIN ASSIGNMENT51820A = Specific Device CodeA= Assembly SiteL= Wafer Lot NumberYW= Assembly Start WeekG= Pb Free Package51820 AALYW GNCP51820(Top View)1234567 SGNDLOSRCLOSNKPGNDHINVBSTVDD813121110915 14 ENLINDTSWVDDLHOSNKVDDHD evicePackageShipping ORDERING INFORMATIONNCP51820 AMNTWGQFN15(Pb Free)4000 / Tape& Reel For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationsBrochure, BRD8011 (Note: Microdot may be in either location) (Top View)1234567 SGNDLOSRCLOSNKPGNDHINVBSTVDD813121110915 14 ENLINDTSWVDDLHOSNKVDDHHOSRCPWMmCorDSPVDD VINPOWERSTAGEENVDDLPGNDDRIVERLINLOSRCSGN DDTVBSTSCHMITTTRIGGER INPUTSHOOT THOUGHPREVENTIONCYCLE By CYCLE EDGETRIGGEREDSHUTDOWNDEAD TIMEMODE CONTROLHINVDDLOLEVEL SHIFTERHOLEVEL (ON/OFF)Figure 1.

4 Typical Application SchematicFigure 2. Internal Block CONNECTIONSNCP51820(Top View)1234567 SGNDLOSRCLOSNKPGNDHINVBSTVDD813121110915 14 ENLINDTSWVDDLHOSNKVDDHF igure 3. Pin Assignments 15 Lead QFN (Top View)HOSRCPIN DESCRIPTIONPin side Driver positive bias voltage output2 HOSRCHigh side Driver sourcing output3 HOSNKHigh side Driver sinking output4 SWSwitch node / high side Driver return5 VDDLLow side Driver positive bias voltage output6 LOSRCLow side Driver sourcing output7 LOSNKLow side Driver sinking output8 PGNDP ower ground / low side Driver return9 DTDead time adjustment / mode select10 SGNDL ogic / signal ground11 LINL ogic input for low side gate Driver output12 HINL ogic input for high side gate Driver output13 ENLogic input for disabling the Driver (low Power mode)14 VDDBias voltage for high current driver15 VBSTB ootstrap positive bias MAXIMUM RATINGS (All voltages are referenced to SGND pin unless otherwise noted)

5 SymbolRatingMinMaxUnitVDDLow side and logic fixed supply voltage (PGND = SGND) side supply voltage VDDL (internally regulated; output only, do not connect to external voltage source, referenced to PGND) side common mode voltage range (SW) side floating supply voltage VDDH (internally regulated; output only, do not connect to external voltage source; referenced to SW) side floating supply voltage VBST side floating supply voltage VBST (referenced to SW) ,VHOSNKHigh side floating Driver sourcing/sinking output voltage (referenced to SW) + voltage ,VLOSNKLow side Driver sourcing/sinking output voltage (referenced to PGND) + input voltage (HIN, LIN, and EN) + time control voltage (DT) + offset voltage slew rate 200V/nsTJOperating Junction Temperature 150 CTSTGS torage Temperature Range 55150 CElectrostatic Discharge CapabilityHuman Body Model (Note 3) 1kVCharged Device Model (Note 3) 1kVStresses exceeding those listed in the Maximum Ratings table may damage the device.

6 If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for SafeOperating VDD PGND voltage must not exceed 20 V3. This device series incorporates ESD protection and is tested by the following methods:ESD Human Body Model tested per ANSI/ESDA/JEDEC JS 001 2012 ESD Charged Device Model tested per JESD22 This device contains latch up protection and exceeds 100 mA per JEDEC Standard JESD78 Class CHARACTERISTICSS ymbolRatingValueUnitqJAThermal Characteristics, QFN15 4x4 (Note 5)Thermal Resistance Junction Ambient (Note 6)IS0P245 C/WIS2P188 PDPower Dissipation (Note 6)QFN15 4x4 (Note 5) Refer to ELECTRICAL CHARACTERISTICS, RECOMMENDED OPERATING RANGES and/or APPLICATION INFORMATION for SafeOperating JEDEC standard: JESD51 2, JESD51 3.

7 Mounted on mm PCB (FR 4 glass epoxy material).IS0P: one single layer with zero Power planesIS2P: one single layer with two Power OPERATING CONDITIONS (All voltages are referenced to SGND pin unless otherwise noted)SymbolRatingMinMaxUnitVDDLow side and logic fixed supply voltage917 VVSW SGNDSW SGND maximum dc offset voltage (High Side Driver ) 580 VVBSTHigh side floating supply voltage VBST VSW+17 VVHOSRC, VHOSNKHigh side floating Driver sourcing/sinking output voltage VDDHVVLOSRC, VLOSNKLow side Driver sourcing/sinking output voltage VDDLVVINL ogic input voltage (HIN, LIN, and EN) 17 VPGND SGNDPGND SGND maximum dc offset voltage (Low Side Driver ) operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyondthe Recommended Operating Ranges limits may affect device CHARACTERISTICS (VBIAS (VDD, VBST) = 15 V, DT = SGND = PGND and CLOAD = 330 pF for typical values TA = 25 C, for min/max values TA = 40 C to +125 C, unless otherwise specified.)

8 The VIN and IIN parameters are referenced to VO and IO parameters are referenced to VSW and PGND and are applicable to the respective outputs HOSRC, HOSNK, LOSRC,and LOSNK. SymbolParameterTest Conditions and DescriptionMinTypMaxUnitPOWER SUPPLY SECTION (VDD)IQDDQ uiescent VDD supply currentVLIN = VHIN = 0 V, EN = 0 V 100150mAIPDDO perating VDD supply currentfLIN = 500 kHz, average value +VDD UVLO positive going thresholdVDD = VDD UVLO negative going thresholdVDD = UVLO HysteresisVDD = Sweep VtUVDDFLTVDD UVLO Filter Delay Time (Note 7) msBOOTSTRAPPED Power SUPPLY SECTIONILKO ffset supply leakage currentVBST = VSW = 600 V 10mAIQBSTQ uiescent VBST supply currentVLIN = VHIN = 0 V, EN = 5 V 35100mAIPBSTO perating VBST supply currentfHIN = 500 kHz, average value +VBST UVLO positive going thresholdVDD = 12 VBST UVLO negative going thresholdVDD = 12 UVLO HysteresisVDD = 12 V VGATE Driver Power SUPPLY SECTIONVDDHVDDH VSW regulated voltage0 mA < IO < 10 PGND regulated LOGIC SECTION (HIN, LIN and EN)

9 VINHHigh Level Input Voltage Threshold Level Input Voltage VVIN_HYSI nput Logic Voltage Hysteresis VIIN+High Level Logic Input Bias CurrentVHIN = VLIN = 5 V91521mAIIN Low Level Logic Input Bias CurrentVHIN = VLIN = 0 V Pull down ResistanceVHIN = VLIN = 5 V 333 kWDEAD TIME SECTIONVDT,MINM inimum Dead Time Control VoltageRDT = 30 , CHARACTERISTICS (VBIAS (VDD, VBST) = 15 V, DT = SGND = PGND and CLOAD = 330 pF for typical values TA = 25 C, for min/max values TA = 40 C to +125 C, unless otherwise specified.) The VIN and IIN parameters are referenced to VO and IO parameters are referenced to VSW and PGND and are applicable to the respective outputs HOSRC, HOSNK, LOSRC,and LOSNK. (continued)SymbolUnitMaxTypMinTest Conditions and DescriptionParameterDEAD TIME SECTIONVDT,MAXM aximum Dead Time Control VoltageRDT = 200 ,MAX160200240nsDtDTDead Time mismatch betweenLO HO and HO LORDT = 30 kW 5nsRDT = 200 kW 10nsVDT,0 Dead Time Disable ThresholdCross conduction prevention ,OLEHigh & Low Side Overlap EnableThresholdCross conduction prevention SECTIONVUVTH_VDDX+UVLO Threshold on VDDH and VDDL positive going UVLO Threshold on VDDH and VDDL negative going Shutdown (Note 7)150 ChysHysteresis of Thermal Shutdown(Note 7) 50 CGATE DRIVE OUTPUT SECTIONVOHHigh level output voltage, VVDDH VHOSRC or VVDDL VLOSRCIOSRC = 10 mA 1040mVVOLLow level output voltage, VHOSNK VSW or VLOSNK PGNDIOSNK = 10 mA 520mVIOSRCPeak source current (Note 7)

10 CLOAD = 200 pF, Rgate = 1 AIOSNKPeak sink current (Note 7)CLOAD = 200 pF, Rgate = 1 AProduct parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different Guaranteed by design, is not tested in ELECTRICAL CHARACTERISTICS (VBIAS (VDD, VBST)=15 V, DT=SGND=PGND and CLOAD=330 pF, for typicalvalues TA=25 C, for min/max values TA= 40 C to +125 C, unless otherwise specified.) (Notes 9) SymbolParameterTest ConditionsMinTypMaxUnitIQDDQ uiescent VDD supply currentVLIN = VHIN = 0 V, EN = 0 V 100150mAtPDLONLOSRC turn on propagation delaytimeLIN rising to LOSRC rising (50% to 10%) 2550nstPDLOFFLOSNK turn off propagation delaytimeLIN falling to LOSNK falling (50% to 90%) 2550nstPDHONHOSRC turn on propagation delaytimeHIN rising to HOSRC rising (50% to 10%)SW = PGND 2550nstPDHOFFHOSNK turn off propagation delaytimeHIN falling to HOSNK falling (50% to 90%)SW = PGND 2550nstRLLOSRC turn on rising time 24nstFLLOSNK turn off falling time turn on rising timeSW = PGND 24nstFHHOSNK turn off falling time ELECTRICAL CHARACTERISTICS (VBIAS (VDD, VBST)=15 V, DT=SGND=PGND and CLOAD=330 pF, for typicalvalues TA=25 C, for min/max values TA= 40 C to +125 C, unless otherwise specified.)