74HC573; 74HCT573 CC • For 74HC573: CMOS level

1 74HC573; 74 HCT573 Octal D-type transparent latch; 3-stateRev. 8 10 September 2021 Product data sheet1. General descriptionThe 74HC573; 74 HCT573 is an 8-bit D-type transparent latch with 3-state outputs. The devicefeatures latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputsenter the latches. In this condition the latches are transparent, a latch output will change each timeits corresponding D-input changes. When LE is LOW the latches store the information that waspresent at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OEcauses the outputs to assume a high-impedance OFF-state.

2 Operation of the OE input does notaffect the state of the latches. Inputs include clamp diodes. This enables the use of current limitingresistors to interface inputs to voltages in excess of Features and benefits Wide supply voltage range from to V CMOS low power dissipation High noise immunity Input levels: For 74HC573: CMOS level For 74 HCT573: TTL level Inputs and outputs on opposite sides of package allowing easy interface with microprocessors Useful as input or output port for microprocessors and microcomputers 3-state non-inverting outputs for bus-oriented applications Common 3-state output enable input Latch-up performance exceeds 100 mA per JESD 78 Class II level B Complies with JEDEC standards.

3 JESD8C ( V to V) JESD7A ( V to V) ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from -40 C to +85 C and from -40 C to +125 C3. Ordering informationTable 1. Ordering informationPackageType numberTemperature rangeNameDescriptionVersion74HC573D74 HCT573D-40 C to +125 CSO20plastic small outline package; 20 leads;body width mmSOT163-174HC573PW74 HCT573PW-40 C to +125 CTSSOP20plastic thin shrink small outline package; 20 leads;body width mmSOT360-174HC573BQ74 HCT573BQ-40 C to +125 CDHVQFN20plastic dual in-line compatible thermal enhancedvery thin quad flat package; no leads; 20 terminals;body mmSOT764-1 Nexperia74HC573; 74 HCT573 Octal D-type transparent latch; 3-state4.

4 Functional diagrammna8093-STATE OUTPUTSLATCH 1 to 8Q0Q1Q2Q3Q4Q5Q6Q71213141516171819D0D1D2D 3D4D5D6D7 LEOE91118 765432 Fig. diagram001aae075Q4D4 DQQ3D3 DQQ2D2 DQQ1D1 DLEQQ0D0 DLATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 QLEOELELELELEQ5D5 DQLATCH 6 LEQ6D6 DQLATCH 7 LEQ7D7 DQLATCH 8 LEFig. diagrammna807D0D1D2D3D4D5D6D7 LEOEQ0Q1Q2Q3Q4Q5Q6Q711112131415161718199 8765432 Fig. symbolmna8081213141516171811C11EN11D1998 765432 Fig. logic symbol74HC_HCT573 All information provided in this document is subject to legal disclaimers. Nexperia 2021. All rights reservedProduct data sheetRev. 8 10 September 20212 / 16 Nexperia74HC573; 74 HCT573 Octal D-type transparent latch; 3-state5.

5 Pinning Pinning001aae076123456789101211141316151 8172019 OEVCCD0Q0D1Q1D2Q2D3Q3D4Q4D5Q5D6Q6D7Q7 GNDLE74HC573 74 HCT573 Fig. configuration SOT163-1 (SO20) andSOT360-1 (TSSOP20)001aae07774HC573 74 HCT573 Transparent top viewQ7D6D7Q6D5Q5D4Q4D3Q3D2Q2D1Q1D0 GND(1)Q0 GNDLEOEVCC912813714615516417318219101112 0terminal 1 index area(1) This is not a ground pin. There is no electrical ormechanical requirement to solder the pad. In casesoldered, the solder land should remain floating orconnected to configuration SOT764-1 (DHVQFN20) Pin descriptionTable 2. Pin descriptionSymbolPinDescriptionOE13-stat e output enable input (active LOW)D0, D1, D2, D3, D4, D5, D6, D72, 3, 4, 5, 6, 7, 8, 9data inputGND10ground (0 V)LE11latch enable input (active HIGH)Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q719, 18, 17, 16, 15, 14, 13, 123-state latch outputVCC20supply voltage74HC_HCT573 All information provided in this document is subject to legal disclaimers.

6 Nexperia 2021. All rights reservedProduct data sheetRev. 8 10 September 20213 / 16 Nexperia74HC573; 74 HCT573 Octal D-type transparent latch; 3-state6. Functional descriptionTable 3. Function tableH = HIGH voltage level ; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition;L = LOW voltage level ; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition;Z = high-impedance modeOELEDnInternal latchesQnLLLE nable and read register(transparent mode)LHHHHlLLLatch and read registerLLhHHlLZLatch register and disable outputsHLhHZ7. Limiting valuesTable 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).

7 Voltages are referenced to GND (ground = 0 V).SymbolParameterConditionsMinMaxUnitVC Csupply +7 VIIK input clamping currentVI < V or VI > VCC + V- 20mAIOK output clamping currentVO < V or VO > VCC + V- 20mAIOoutput currentVO = V to (VCC + V)- 35mAICC supply current-+70mAIGND ground current-70-mATstgstorage temperature-65+150 CPtottotal power dissipation[1]-500mW[1]For SOT163-1 (SO20) package: Ptot derates linearly with mW/K above 109 SOT360-1 (TSSOP20) package: Ptot derates linearly with mW/K above 100 SOT764-1 (DHVQFN20) package: Ptot derates linearly with mW/K above 111 Recommended operating conditionsTable 5.

8 Recommended operating conditionsVoltages are referenced to GND (ground = 0 V)74HC57374 HCT573 SymbolParameterConditionsMinTypMaxMinTyp MaxUnitVCCsupply voltage0-VCC0-VCCVVO output voltage0-VCC0-VCCVT ambambient temperature-40+25+125-40+25+125 CVCC = V--625---ns/VVCC = t/ Vinput transition rise and fallrateVCC = V--83---ns/V74HC_HCT573 All information provided in this document is subject to legal disclaimers. Nexperia 2021. All rights reservedProduct data sheetRev. 8 10 September 20214 / 16 Nexperia74HC573; 74 HCT573 Octal D-type transparent latch; 3-state9. Static characteristicsTable 6. Static characteristicsAt recommended operating conditions; voltages are referenced to GND (ground = 0 V).

9 25 C-40 C to+85 C-40 C to+125 CSymbolParameterConditionsMinTypMaxMinMa xMinMaxUnit74HC573 VCC = = voltageVCC = = = voltageVCC = = VIH or VILIO = -20 A; VCC = = -20 A; VCC = = -20 A; VCC = = mA; VCC = voltageIO = mA; VCC = = VIH or VILIO = 20 A; VCC = = 20 A; VCC = = 20 A; VCC = = mA; VCC = voltageIO = mA; VCC = leakagecurrentVI = VCC or GND; VCC = V-- AIOZOFF-stateoutput currentVI = VIH or VIL; VCC = V;VO = VCC or GND-- AICC supply currentVI = VCC or GND; IO = 0 A;VCC = voltageVCC = V to voltageVCC = V to = VIH or VIL; VCC = VIO = -20 voltageIO = -6 = VIH or VIL; VCC = VIO = 20 voltageIO = information provided in this document is subject to legal disclaimers.

10 Nexperia 2021. All rights reservedProduct data sheetRev. 8 10 September 20215 / 16 Nexperia74HC573; 74 HCT573 Octal D-type transparent latch; 3-state25 C-40 C to+85 C-40 C to+125 CSymbolParameterConditionsMinTypMaxMinMa xMinMaxUnitIIinput leakagecurrentVI = VCC or GND; VCC = V-- AIOZOFF-stateoutput currentVI = VIH or VIL; VCC = V;VO = VCC or GND-- 10 AICC supply currentVI = VCC or GND; IO = 0 A;VCC = AVI = VCC - V;other inputs at VCC or GND;VCC = V to V; IO = 0 Aper input pin; Dn inputs-35126-158-172 Aper input pin; LE input-65234-293-319 A ICCadditionalsupply currentper input pin; OE input-125450-563-613 Dynamic characteristicsTable 7.