A CAN Physical Layer Discussion

1 2002 Microchip Technology 1 MAN228 INTRODUCTIONMany network protocols are described using the sevenlayer Open System Interconnection (OSI) model, asshown in Figure 1. The Controller Area Network (CAN)protocol defines the Data Link Layer and part of thePhysical Layer in the OSI model. The remaining physi-cal Layer (and all of the higher layers) are not defined bythe CAN specification. These other layers can either bedefined by the system designer, or they can be imple-mented using existing non-proprietary Higher LayerProtocols (HLPs) and Physical Data Link Layer is defined by the CAN specifica-tion. The Logical Link Control (LLC) manages the over-load control and notification, message filtering andrecovery management functions. The Medium AccessControl (MAC) performs the data encapsulation/decap-sulation, error detection and control, bit stuffing/de-stuffing and the serialization and Physical Medium Attachment (PMA) and MediumDependent Interface (MDI) are the two parts of thephysical Layer which are not defined by CAN.

2 ThePhysical Signaling (PS) portion of the Physical Layer isdefined by the CAN specification. The system designercan choose any driver/receiver and transport mediumas long as the PS requirements are International Standards Organization (ISO) hasdefined a standard which incorporates the CAN speci-fication as well as the Physical Layer . The standard,ISO-11898, was originally created for high-speed in-vehicle communications using CAN. ISO-11898 speci-fies the Physical Layer to ensure compatibility betweenCAN CAN controller typically implements the entire CANspecification in hardware, as shown in Figure 1. ThePMA is not defined by CAN, however, it is defined byISO-11898. This document discusses the MCP2551 CAN transceiver and how it fits in with the 1:CAN AND THE OSI MODELA uthor:Pat RichardsMicrochip Technology LinkPhysical Medium AttachmentPhysical SignalingMedium Dependent Interface- Bit encoding/decoding- Bit timing/synchronization- Driver/receiver characteristics- Connectors/wiresLogical Link Control (LLC)Medium Access Control (MAC)- Data encapsulation/decapsulation- Acceptance filtering- Overload notification- Recovery management- Frame coding (stuffing/de-stuffing)- Error detection/signaling- Serialization/deserializationDefined byISO118987- Layer OSICAN ControllerTransceiverMCP2551A CAN Physical Layer DiscussionAN228DS00228A-page 2 Preliminary 2002 Microchip Technology OVERVIEWISO11898 is the international standard for high-speedCAN communications in road vehicles.

3 ISO-11898-2specifies the PMA and MDA sublayers of the PhysicalLayer. See Figure 3 for a representation of a commonCAN node/bus as described by LevelsCAN specifies two logical states: recessive and domi-nant. ISO-11898 defines a differential voltage to repre-sent recessive and dominant states (or bits), as shownin Figure the recessive state ( , logic 1 on the MCP2551 TXD input), the differential voltage on CANH and CANLis less than the minimum threshold (< receiverinput or < transmitter output)(See Figure 4).In the dominant state ( , logic 0 on the MCP2551 TXD input), the differential voltage on CANH and CANLis greater than the minimum threshold. A dominant bitoverdrives a recessive bit on the bus to achievenondestructive bitwise 2:DIFFERENTIAL BUSC onnectors and WiresISO-11898-2 does not specify the mechanical wiresand connectors. However, the specification doesrequire that the wires and connectors meet the electri-cal specification also requires 120 (nominal) termi-nating resistors at each end of the bus.

4 Figure 3 showsan example of a CAN bus based on 3:CAN BUSV oltage Level (V)Time (t)VDIFFD ominantRecessiveRecessiveCANHCANL120 120 MCUCAN ControllerTransceiverNodeNode 2002 Microchip Technology 3AN228 FIGURE 4:ISO11898 NOMINAL BUS LEVELSR obustnessThe ISO11898-2 specification requires that a compliantor compatible transceiver must meet a number of elec-trical specifications. Some of these specifications areintended to ensure the transceiver can survive harshelectrical conditions, thereby protecting thecommunications of the CAN node. The transceivermust survive short circuits on the CAN bus inputs from-3V to +32V and transient voltages from -150V to+100V. Table 1 shows the major ISO11898-2 electricalrequirements, as well as MCP2551 1:COMPARING THE MCP2551 TO Voltage on CANH and CANL-3+32-40+40 VExceeds ISO-11898 Transient voltage on CANH and CANL-150+100-250+250 VExceeds ISO-11898 Common Mode Bus + +12 VExceeds ISO-11898 Recessive Output Bus Voltage+ + + + ISO-11898 Recessive Differential Output Voltage-500+50-500+50mV Meets ISO-11898 Differential Internal Resistance1010020100k Meets ISO-11898 Common Mode Input Meets ISO-11898 Differential Dominant Output Voltage+ + + + ISO-11898 Dominant Output Voltage (CANH)+ + + + ISO-11898 Dominant Output Voltage (CANL)+ + + + ISO-11898 Permanent Dominant Detection (Driver)Not msPower-On Reset and Brown-Out DetectionNot RequiredYe s- -AN228DS00228A-page 4 Preliminary 2002 Microchip Technology LengthsISO11898 specifies that a transceiver must be able todrive a 40m bus at 1 Mb/s.

5 A longer bus length can beachieved by slowing the data rate. The biggest limita-tion to bus length is the transceiver s DELAYThe CAN protocol has defined a recessive (logic 1 )and dominant (logic 0 ) state to implement a non-destructive bit-wise arbitration scheme. It is this arbitra-tion methodology that is affected most by propagationdelays. Each node involved with arbitration must beable to sample each bit level within the same bit example, if two nodes at opposite ends of the busstart to transmit their messages at the same time, theymust arbitrate for control of the bus. This arbitration isonly effective if both nodes are able to sample duringthe same bit time. Figure 5 shows a one-way propaga-tion delay between two nodes. Extreme propagationdelays (beyond the sample point) will result in invalidarbitration. This implies that bus lengths are limited atgiven CAN data CAN system s propagation delay is calculated asbeing a signal s round-trip time on the Physical bus(tbus), the output driver delay (tdrv) and the input com-parator delay (tcmp).

6 Assuming all nodes in the systemhave similar component delays, the propagation delayis explained mathematically:EQUATION 1:FIGURE 5:ONE-WAY PROPAGATION DELAY tprop2tbustcmptdrv++() =SyncSegSample PointSyncSegTransmitted Bit from Node A Node A bit received by Node B Propagation DelayTime (t)PropSegPhaseSeg1 (PS1)PhaseSeg2 (PS2)PropSegPhaseSeg1 (PS1)PhaseSeg2 (PS2) 2002 Microchip Technology 5AN228 MCP2551 CAN TRANSCEIVERThe MCP2551 is a CAN Transceiver that implementsthe ISO-11898-2 Physical Layer specification. It sup-ports a 1 Mb/s data rate and is suitable for 12 V and 24V systems. The MCP2551 provides short-circuitprotection up to 40V and transient protection up to addition to being ISO-11898-2-compatible, theMCP2551 provides power-on reset and brown-out pro-tection, as well as permanent dominant detection toensure an unpowered or faulty node will not disturb thebus.

7 The device implements configurable slope controlon the bus pins to help reduce RFI emissions. Figure6 shows the block diagram of the MCP2551 OperationTRANSMITThe CAN protocol controller outputs a serial datastream to the logic TXD input of the MCP2551. The cor-responding recessive or dominant state is output on theCANH and CANL MCP2551 receives dominant or recessive stateson the same CANH and CANL pins as the transmitoccurs. These states are output as logic levels on theRXD pin for the CAN protocol controller to receive STATEA logic 1 on the TXD input turns off the drivers to theCANH and CANL pins and the pins float to a via biasing STATEA logic 0 on the TXD input turns on the CANH andCANL pin drivers. CANH drives ~1V higher than thenominal recessive state to ~ CANL drives~1V less than the nominal recessive state to~ 6:MCP2551 BLOCK DIAGRAMVDDVSSCANHCANLTXDRSRXDVREFVDDS lope VDDTXDD ominantDetectThermalShutdownDriverContro lAN228DS00228A-page 6 Preliminary 2002 Microchip Technology of OperationThere are three modes of operation that are externallycontrolled via the RS high-speed mode is selected by connecting the RSpin to VSS.

8 In this mode, the output drivers have fastrise and fall times that support the higher bus rates upto 1 Mb/s and/or maximum bus lengths by providing theminimum transceiver loop CONTROLIf reduced EMI is required, the MCP2551 can be placedin slope control mode by connecting a resistor (REXT)from the RS pin to ground. In slope control mode, thesingle-ended slew rate (CANH or CANL) is basicallyproportional to the current out of the RS pin. The currentmust be in the range of 10 A < -IRS < 200 A, whichcorresponds to a voltage on the pin of VDD < VRS < VDD respectively (or VDD typical).The decreased slew rate implies a slower CAN datarate at a given bus length, or a reduced bus length at agiven CAN data (or sleep) mode is entered by connecting theRS pin to VDD. In sleep mode, the transmitter isswitched off and the receiver operates in a reducedpower mode.

9 While the receive pin (RXD) is stillfunctional, it will operate at a slower mode can be used to place the device in lowpower mode and to turn off the transmitter in case theCAN controller malfunctions and sends unexpecteddata to the Dominant Detection on TransmitterThe MCP2551 will turn off the transmitter to CANH andCANL if an extended dominant state is detected on thetransmitter. This ability prevents a faulty node (CANcontroller or MCP2551) from permanently corruptingthe CAN drivers are disabled if TXD is low for more than~ ms (minimum) (See Figure 7).The drivers will remain disabled as long as TXDremains low. A rising edge on TXD will reset the timerlogic and enable the 7:TXD PERMANENT DOMINANT DETECTIOND ominantRecessivetDOMT ransmitterDisabledTransmitterEnabledRece ssiveDominantTXDCANHCANL 2002 Microchip Technology 7AN228 Power-On Reset and Brown-OutThe MCP2551 incorporates both Power-On Reset(POR) and Brown-Out Detection (BOD) (see Figure 8).

10 POWER-ON RESET (POR)When the MCP2551 is powered on, the CANH andCANL pins remain in the high impedance state untilVDD reaches the POR high voltage (VPORH).Additionally, if the TXD pin is low at power-up, theCANH and CANL pins will remain in high impedanceuntil TXD goes high. After which, the drivers willfunction DETECTION (BOD)BOD occurs when VDD goes below the power-on resetlow voltage (VPORL). At this point, the CANH and CANL pins enter a high impedance state and will remain thereuntil VPORH is 8:POWER-ON RESET AND BROWN-OUT 8 Preliminary 2002 Microchip Technology OffsetsSince it is not required to provide a common groundbetween nodes, it is possible to have ground offsetsbetween nodes. That is, each node may observe differ-ent single-ended bus voltages (common mode busvoltages) while maintaining the same differential volt-age.