AR0130CS - 1/3‐inch CMOS Digital Image Sensor

1 Semiconductor Components Industries, LLC, 2016 March, 2018 Rev. 141 Publication Order Number: AR0130CS /DAR0130CS1/3 inch CMOS DigitalImage SensorDescriptionON Semiconductor AR0130 is a 1/3 inch CMOS Digital imagesensor with an active pixel array of 1280H x 960V. It captures imageswith a rolling shutter readout. It includes sophisticated camerafunctions such as auto exposure control, windowing, and both videoand single frame modes. It is programmable through a simpletwo wire serial interface. The AR0130 produces extraordinarily clear,sharp Digital pictures, and its ability to capture both continuous videoand single frames makes it the perfect choice for a wide range ofapplications, including gaming systems, surveillance, and HD 1.

2 KEY PERFORMANCE PARAMETERS ParameterTypical ValueOptical Format1/3-inch (6 mm)Active Pixels1280 (H) 960 (V) = MpPixel Filter ArrayMonochrome, RGB BayerShutter TypeElectronic Rolling ShutterInput Clock Range6 50 MHzOutput Clock MHzOutputParallel12-bitMax. Frame Mp (Full FOV)720p HD (Reduced FOV)VGA (Full FOV)VGA (Reduced FOV)800 x 800 (Reduced FOV)45 fps60 fps45 fps60 fps60 fpsResponsivity at 550 nmMonochromeRGB V/lux V/lux secSNRMAX44 dBDynamic Range82 dBSupply or VPower Consumption270 mW (1280 x 720 60 fps)Operating Temperature 30 C to + 70 C (Ambient) 30 C to + 80 C (Junction)Package Options PLCC10 10 mm 48-pin iLCCBare Superior Low-light Performance Both inVGA Mode and HD Mode Excellent Near IR Performance HD Video (720p60) On-chip AE and Statistics Engine Auto Black Level Calibration Context Switching Progressive Scan Supports 2.

3 1 Scaling Internal Master Clock Generated byOn chip Phase Locked Loop (PLL)Oscillator Parallel OutputApplications Gaming Systems Video Surveillance 720p60 Video ApplicationsSee detailed ordering and shipping information on page 2 ofthis data INFORMATIONPLCC48 y 776 ALILCC48 10 y 10 CASE INFORMATIONT able 2. ORDERABLE PART NUMBERS Part NumberBase DescriptionVariant DescriptionAR0130 CSSC00 SPBA0 DP1 RGB Bayer 48 Pin PLCCDry Pack with Protective FilmAR0130 CSSC00 SPBA0 DR1 RGB Bayer 48 Pin PLCCDry Pack without Protective FilmAR0130 CSSC00 SPCA0 DPBR1 RGB Bayer 48 Pin iLCCDry Pack with Protective Film, Double Side BBAR GlassAR0130 CSSC00 SPCA0 DRBR1 RGB Bayer 48 Pin iLCCDry Pack without Protective Film, Double Side BBAR GlassAR0130 CSSC00 SPCAH GEVBRGB Bayer headboard iLCCAR0130 CSSC00 SPCAH S115 GEVBRGB Bayer headboard iLCCAR0130 CSSC00 SPCAH S213A GEVBRGB Bayer headboard iLCCAR0130 CSSC00 SPCAW GEVBRGB Bayer headboard iLCCAR0130 CSSM00 SPCA0 DRBR1 Monochrome 48 Pin iLCCDry Pack without Protective Film.

4 Double Side BBAR GlassAR0130 CSSM00 SPCAH S213A GEVBM onochrome headboard iLCCSee the ON Semiconductor Device Nomenclaturedocument (TND310/D) for a full description of the namingconvention used for Image sensors. For referencedocumentation, including information on evaluation kits,please visit our web site at DESCRIPTIONThe ON Semiconductor AR0130 can be operated in itsdefault mode or programmed for frame size, exposure, gain,and other parameters. The default mode output is a960p resolution Image at 45 frames per second (fps). Itoutputs 12 bit raw data over the parallel port. The devicemay be operated in video (master) mode or in single frametrigger and LINE_VALID signals are output ondedicated pins, along with a synchronized pixel clock inparallel AR0130 includes additional features to allowapplication specific tuning: windowing and offset,adjustable auto exposure control, and auto black levelcorrection.

5 Optional register information and histogramstatistic information can be embedded in first and last 2 linesof the Image OVERVIEWThe AR0130 is a progressive scan Sensor that generatesa stream of pixel data at a constant frame rate. It uses anon chip, phase locked loop (PLL) that can be optionallyenabled to generate all internal clocks from a single masterinput clock running between 6 and 50 MHz The maximumoutput pixel rate is Mp/s, corresponding to a clock rateof MHz. Figure 1 shows a block diagram of the 1. Block DiagramControl RegistersAnalog Processing andA/D ConversionActive Pixel Sensor (APS)ArrayPixel Data Path(Signal Processing)Timing and Control(Sequencer)Auto Exposureand Stats EngineOTPMM emoryPLLE xternalClockParallel OutputTriggerTwo-wireSerialInterfacePowe rUser interaction with the Sensor is through the two wireserial bus, which communicates with the array control,analog signal chain, and Digital signal chain.

6 The core of thesensor is a Mp Active Pixel Sensor array. The timingand control circuitry sequences through the rows of thearray, resetting and then reading each row in turn. In the timeinterval between resetting a row and reading that row, thepixels in the row integrate incident light. The exposure iscontrolled by varying the time interval between reset andreadout. Once a row has been read, the data from thecolumns is sequenced through an analog signal chain(providing offset correction and gain), and then through ananalog to Digital converter (ADC). The output from theADC is a 12 bit value for each pixel in the array. The ADCoutput passes through a Digital processing signal chain(which provides further data path corrections and appliesdigital gain).

7 The pixel data are output at a rate of up Mp/s, in parallel to frame and line 2. Typical Configuration: Parallel Pixel Data InterfaceVAA_PIXVAAVDD_PLLVDDVDD_IOFrom ControllerMaster Clock(6 50 MHz) kW kW 2,3 DigitalI/OPower1 DigitalCorePower1 PLLP ower1 AnalogPower1 SDATASADDRSCLKTRIGGEROE_BARSTANDBYRESET_ BARR eservedDOUT [11:0]PIXCLKFRAME_VALIDLINE_VALIDA nalogPower1 DGNDAGNDD igitalGroundAnalogGroundVAAVAA_PIXVDD_PL LVDD_IO VDDEXTCLKTo ControllerNotes:1. All power supplies must be adequately ON Semiconductor recommends a resistor value of kW, but a greater value may be used for slower two wire This pull up resistor is not required if the controller drives a valid logic level on SCLK at all ON Semiconductor recommends that VDD_SLVS pad (only available in bare die) is left ON Semiconductor recommends that mF and 10 mF decoupling capacitors for each power supply are mounted as close as possible to the pad.

8 Actual values and results may vary depending on layout and design considerations. Check the AR0130 demo headboard schematics for circuit ON Semiconductor recommends that analog power planes are placed in a manner such that coupling with the Digital power planes is I/O signals voltage must be configured to match VDD_IO voltage to minimize any leakage 3. PAD DESCRIPTIONSNameTypeDescriptionSTANDBYI nputStandby mode enable pin (active HIGH).VDD_PLLP owerPLL input power (do not connect).DGNDP owerDigital Wire Serial Interface address Wire Serial Interface clock Wire Serial Interface data 3. PAD DESCRIPTIONSD escriptionTypeNameVAA_PIXP owerPixel when DOUT line data is when DOUT frame data is clock out.

9 DOUT is valid on rising edge of this supply pixel data pixel data pixel data pixel data output (MSB)ReservedInputConnect to pixel data pixel data pixel data pixel data synchronization enable (active LOW).DOUT0 OutputParallel pixel data output (LSB)DOUT1 OutputParallel pixel data pixel data pixel data reset (active LOW). All settings are restored to factory control not 3. 48 Pin iLCC Pinout 4. 48 Pin PLCC Pinout DiagramTop DATA FORMATP ixel Array StructureThe AR0130 pixel array is configured as 1412 columns by1028 rows, (see Figure 5). The dark pixels are opticallyblack and are used internally to monitor black level. Of theright 108 columns, 64 are dark pixels used for row noisecorrection.

10 Of the top 24 rows of pixels, 12 of the dark rowsare used for black level correction. There are 1296 columnsby 976 rows of optically active pixels. While the Sensor sformat is 1280 x 960, the additional active columns andactive rows are included for use when horizontal or verticalmirrored readout is enabled, to allow readout to start on thesame pixel. The pixel adjustment is always performed formonochrome or color versions. The active area issurrounded with optically transparent dummy pixels toimprove Image uniformity within the active area. Not alldummy pixels or barrier pixels can be read 5. Pixel Array Description14121028 Dark PixelBarrier PixelLight DummyPixelActive Pixel2 Light Dummy + 4 Barrier + 24 Dark + 4 Barrier +6 Dark Dummy1296 976 (1288 968 Active) mm2 ( mm2)2 Light Dummy + 4 Barrier + 100 Dark + 4 Barrier2 Light Dummy + 4 Barrier2 Light Dummy + 4 Barrier + 6 Dark DummyFigure 6.