Data Sheet ADIN2111 - analog.com

1 Data SheetADIN2111 Low Complexity, 2-Port Ethernet Switch with Integrated 10 BASE-T1L PHYsRev. 0 DOCUMENT FEEDBACK TECHNICAL SUPPORTI nformation furnished by analog Devices is believed to be accurate and reliable "as is". However, no responsibility is assumed by AnalogDevices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject tochange without notice. No license is granted by implication or otherwise under any patent or patent rights of analog Devices. Trademarks andregistered trademarks are the property of their respective 10 BASE-T1L IEEE Standard compliant Supports V p-p and V p-p transmit levels Cable reach Up to 1700 meters with V p-p transmit level Up to 1700 meters with V p-p transmit level Low power consumption Single supply V p-p: 90 mW typical dual supply V p-p.

2 77 mW typical Integrated switch with SPI 10 Mbps full duplex 16 MAC addresses supported for frame forwarding Supports OPEN Alliance 10 BASE-T1x MACPHY SPI MDIO memory map accessible via SPI Supports high and low priority queues Total buffer memory of 28 kB shared between ports and host Autonegotiation capability Managed or unmanaged configuration Cut through or store and forward operation IEEE 1588 time stamp capture on transmit and receive Diagnostics Frame generator and checker Multiple loopback modes IEEE test mode support Port dedicated statistics counters Link and cable diagnostics 25 MHz crystal or external clock input Single or dual supply with V or V operation Integrated power supply monitoring and POR Small package: 48-lead, 7 mm 7 mm LFCSP Temperature range Industrial: 40 C to +85 C Extended: 40 C to +105 CAPPLICATIONS Building automation and fire safety Factory automation Edge sensors and actuators Condition monitoring and machine connectivityFUNCTIONAL BLOCK DIAGRAMF igure DESCRIPTIONThe ADIN2111 is a low power, low complexity, two-Ethernet portsswitch with integrated 10 BASE-T1L PHYs and one serial peripheralinterface (SPI) port.

3 The device is designed for industrial Ethernetapplications using low power constrained nodes and is compliantwith the IEEE Ethernet standard for long reach10 Mbps single pair Ethernet (SPE). The switch (cut through orstore and forward) supports various routing configurations betweenthe two Ethernet ports and the SPI host port providing a flexiblesolution for line, daisy-chain, or ring network ADIN2111 supports cable reach of up to 1700 meters with ultralow power consumption of 77 mW. The two PHY cores supportthe V p-p operating mode and the V p-p operating modedefined in the IEEE standard, and can operate from asingle power supply rail of V or V.

4 The ADIN2111 can beused in unmanaged configurations where the device automaticallyforwards the traffic between the two Ethernet device integrates the switch, two Ethernet physical layer (PHY)cores with a media access control (MAC) interface and all the asso-ciated analog circuitry, and input and output clock buffering. Thedevice also includes internal buffer queues, the SPI and subsystemregisters, as well as the control logic to manage the reset and clockcontrol and hardware pin ADIN2111 has an integrated voltage supply monitoring circuitand power-on reset (POR) circuitry to improve system level robust-ness. The 4-wire SPI for communication with the host can beconfigured to OPEN Alliance SPI or generic SPI.

5 Both modessupport optional data protection or cyclic redundancy check (CRC). analog Devices is in the process of updating documentation to provide terminology and language that is culturally appropriate. This is a processwith a wide scope and will be phased in as quickly as possible. Thank you for your SheetADIN2111 TABLE OF 0 | 2 of 1 Functional Block 3 Timing Maximum 7 Electrostatic Discharge (ESD) Configuration and Function 8 Typical Performance 11 Theory of 12 Power Supply Port Amplitude Interrupt (INT)..16 Reset 17 Status 18 Power-Down Configuration 21 Managed Configuration Pin Up 10 BASE-T1L 23 Unmanaged PHY PHY Generator and 28 Frame Generator and Checker Link 31 System Level Power Daisy Chain, Line, and RingNetwork Circuit 32 Component 35 Generic SPI Alliance SPI Forwarding on Priority 45 Frame Receive and Transmit 46 SPI Access to the PHY 50 SPI Register Map.

6 50 PHY Clause 22 Register Details .. 84 PHY Clause 45 Register Details .. 87 PCB Layout 124 Land Placement and 124 Crystal Placement and 125 Ordering HISTORY12/2021 Revision 0: Initial VersionData 0 | 3 of 125 AVDD_H = AVDD_L = VDDIO = V, DVDD_1P1 from internal low dropout (LDO) regulator (DVDD_1P1 = DLDO_1P1), and all specificationsat 40 C to +105 C, unless otherwise 1. General SpecificationsParameterMinTypMaxUnitTest Conditions/CommentsDIGITAL INPUTS/OUTPUTSA pplies to the SPI pins, INT, RESET, and Px_LED_0 andPx_LED_1 pinsVDDIO = VInput Low Voltage (VIL) High Voltage (VIH) Low Voltage (VOL) low current (IOL) (minimum) = 2 mAOutput High Voltage (VOH) high current (IOH) (minimum) = 2 mAVDDIO = (minimum) = 2 (minimum) = 2 mAVDDIO = VDDIOVIOL (minimum) = 2 VDDIOVIOH (minimum) = 2 mARESET Deglitch sLED OUTPUTO utput Drive Current8mAVDDIO = V6mAVDDIO = V4mAVDDIO = VCLOCKSE xternal Crystal (XTAL)

7 Requirements for external crystal used on XTAL_I/CLK_INpin and XTAL_O pinCrystal Frequency25 MHzCrystal Frequency Tolerance 30+30ppmCrystal Drive Level<200 WCrystal Equivalent Series Resistance (ESR)60 XTAL_I, XTAL_O Input Capacitance (CIN,EQ) parallel differential input capacitance looking intoXTAL_I/CLK_IN pin and XTAL_O pinCrystal Load Capacitance (CL)11018pFIncluding PCB trace capacitance and XTAL_I, XTAL_OCIN,EQStart-Up Time2msCrystal oscillator onlyClock Input (CLK_IN) clock Input Frequency25 MHzRequirements for external clock applied to XTAL_I pinClock Input Voltage p-pAC-coupled sine or square wave at XTAL_I/CLK_IN pinClock Input Duty Cycle4555%Input clock duty cycle 50%XTAL_I Input Impedance (ZIN,EQ)Driving Point Resistance (RP)26k RP||CPDriving Point Capacitance (CP)23pFJitter Tolerance (RMS)40psCLK25_REF clock OutputCLK25_REF = 10 pFVOL0 VLoad = 10 pFCLK25_REF Duty Cycle4555%Load = 10 pFData 0 | 4 of 125 Table 1.

8 General SpecificationsParameterMinTypMaxUnitTest Conditions/CommentsCLK25_REF Frequency Tolerance 50+50ppmLong-Term Jitter (RMS)40ps1 Load capacitance (CL) = ((C1 C2)/(C1 + C2) + CSTRAY), where CSTRAY is the stray capacitance including routing and package and CP are the values of the equivalent parallel RC circuit to ac ground (RP||CP), modeling the driving point impedance of the XTAL_I/CLK_IN 2. 10 BASE-T1L SpecificationsParameterMinTypMaxUnitTest Conditions/CommentsPOWER REQUIREMENTSS upply Voltage V p-p or V p-p transmit or , , , or V p-p Transmit Level (Single Supply)AVDD_H = AVDD_L = VDDIO = V, DVDD_1P1 = DLDO_1P1 AVDD_H/AVDD_L/VDDIO Supply Current(IAVDD_H/ IAVDD_L/IVDDIO)50mAMeasured current (Imeasured) = IAVDD_H + IAVDD_L + IVDDIOP ower Consumption90mW100% data throughput, full activity22mWSoftware power-down V p-p Transmit Level ( dual Supply)AVDD_H = AVDD_L = VDDIO = V, DVDD_1P1 = external VAVDD_H/AVDD_L/VDDIO Supply Current30mAImeasured = IAVDD_H + IAVDD_L + IVDDIODVDD Supply Current (IDVDD)

9 20mASupply for DVDD1_1P1 and DVDD2_1P1 pins, Imeasured = IDVDDP ower Consumption77mW100% data throughput, full V p-p Transmit Level (Single Supply)AVDD_H = AVDD_L = VDDIO = V, DVDD_1P1 = DLDO_1P1 AVDD_H/AVDD_L/VDDIO Supply Current65mAImeasured = IAVDD_H + IAVDD_L + IVDDIOP ower Consumption215mW100% data throughput, full activity44mWSoftware power-down V p-p Transmit Level ( dual Supply)AVDD_H = V, AVDD_L = VDDIO = V, DVDD_1P1 =DLDO_1P1 AVDD_H Supply = IAVDD_HAVDD_L/VDDIO Supply Current30mAImeasured= IAVDD_L + IVDDIOP ower Consumption162mW100% data throughput, full activity22mWSoftware power-down V p-p Transmit Level (Triple Supply)

10 AVDD_H = V, AVDD_L = VDDIO = V, DVDD_1P1 = VAVDD_H Supply Current33mAImeasured = IAVDD_HAVDD_L/VDDIO Supply Current10mAImeasured = IAVDD_L + IVDDIODVDD Supply Current20mAExternal supply for DVDD1_1P1 and DVDD2_1P1 pins, Imeasured =IDVDDP ower Consumption149mW100% data throughput, full activityTIMING/LATENCYPort to Port LatencyPHY sPHY 1 or PHY 2 Rx sPHY sPHY 1 or PHY 2 Tx latencyTotal sSystem/PHY 1 Reset to Standby Delay50msDelay after RESET pin released; internal MAC registers and Port 1 PHY registers accessiblePHY 2 Reset to Standby Delay90msDelay after RESET pin released and Port 2 PHY registers accessibleData SheetADIN2111 TIMING 0 | 5 of 125 POWER-UP TIMINGT able 3.