EEPROM Serial 256-Kb I2C

1 DATA Semiconductor Components Industries, LLC, 2014 February, 2022 Rev. 161 Publication Order Number:CAT24C256/DEEPROM Serial 256-Kb I2 CCAT24C256 DescriptionThe CAT24C256 is a EEPROM Serial 256 Kb I2C, internallyorganized as 32,768 words of 8 bits features a 64 byte page write buffer and supports the Standard(100 kHz), Fast (400 kHz) and Fast Plus (1 MHz) I2C operations can be inhibited by taking the WP pin High (thisprotects the entire memory).External address pins make it possible to address up to eightCAT24C256 devices on the same Chip ECC (Error Correction Code) makes the device suitablefor high reliability Supports Standard, Fast and Fast Plus I2C Protocol V to V Supply Voltage Range 64 Byte Page Write Buffer Hardware Write Protection for Entire Memory Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs(SCL and SDA) Low Power CMOS Technology 1,000,000 Program/Erase Cycles 100 Year Data Retention Industrial and Extended Temperature Range SOIC, TSSOP and UDFN 8 Pad Packages This Device is Pb Free, Halogen Free/BFR Free, and RoHSCompliantFigure 1.

2 Functional SymbolSDASCLWPCAT24C256 VCCVSSA2, A1, A0 PIN CONFIGURATIONSDAWPVCCVSSA2A1A01 See detailed ordering and shipping information in the packagedimensions section on page 9 of this data INFORMATIONSOIC 8W SUFFIXCASE 751 BDSCLSOIC (W, X), TSSOP (Y), UDFN (HU4)TSSOP 8Y SUFFIXCASE 948 ALDevice AddressA0, A1, A2 Serial DataSDAS erial ClockSCLW rite ProtectWPPower SupplyVCCG roundVSSF unctionPin Name PIN FUNCTIONFor the location of Pin 1, please consult thecorresponding package 8HU4 SUFFIXCASE 517AZ The exposed pad for the UDFN packages can be leftfloating or connected to 1. ABSOLUTE MAXIMUM RATINGSP arametersRatingsUnitsStorage Temperature 65 to +150 CVoltage on any Pin with Respect to Ground (Note 1) to + exceeding those listed in the Maximum Ratings table may damage the device.

3 If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be The DC input voltage on any pin should not be lower than V or higher than VCC + V. During transitions, the voltage on any pin mayundershoot to no less than V or overshoot to no more than VCC + V, for periods of less than 20 2. RELIABILITY CHARACTERISTICS (Note 2)SymbolParameterMinUnitsNEND (Notes 3, 4)Endurance1,000,000 Program/Erase CyclesTDRData Retention100 Years2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC Q100and JEDEC test Page Mode, VCC = 5 V, 25 The product uses ECC (Error Correction Code) logic with 6 ECC bits to correct one bit error in 4 data bytes.

4 Therefore, when a single bytehas to be written, 4 bytes (including the ECC bits) are re programmed. It is recommended to write by multiple of 4 bytes in order to benefitfrom the maximum number of write 3. OPERATING CHARACTERISTICS(VCC = V to V, TA = 40 C to +85 C and VCC = V to V, TA = 40 C to +125 C, unless otherwise specified.)SymbolParameterTest ConditionsMinMaxUnitsICCRRead CurrentRead, fSCL = 400 kHz/1 MHz1mAICCWW rite Current3mAISBS tandby CurrentAll I/O Pins at GND or VCCTA = 40 C to +85 C2mATA = 40 C to +125 C5 ILI/O Pin LeakagePin at GND or VCCTA = 40 C to +85 C1mATA = 40 C to +125 C2 VIL1 Input Low V VCC V VCCVVIL2 Input Low V VCC < V VCCVVIH1 Input High V VCC VCCVCC + High V VCC < VCCVCC + Low VoltageVCC V, IOL = Low VoltageVCC < V, IOL = parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.

5 Productperformance may not be indicated by the Electrical Characteristics if operated under different 4. PIN IMPEDANCE CHARACTERISTICS(VCC = V to V, TA = 40 C to +85 C and VCC = V to V, TA = 40 C to +125 C, unless otherwise specified.)SymbolParameterConditionsMaxU nitsCIN (Note 5)SDA I/O Pin CapacitanceVIN = 0 V8pFCIN (Note 5)Input Capacitance (other pins)VIN = 0 V6pFIWP, IA (Note 6)WP Input Current, Address InputCurrent (A0, A1, A2)VIN < VIH, VCC = V75mAVIN < VIH, VCC = V50 VIN < VIH, VCC = V25 VIN > VIH25. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC Q100and JEDEC test When not driven, the WP, A0, A1, A2 pins are pulled down to GND internally.

6 For improved noise immunity, the internal pull down is relativelystrong; therefore the external driver must be able to supply the pull down current when attempting to drive the input HIGH. To conserve power,as the input level exceeds the trip point of the CMOS input buffer (~ x VCC), the strong pull down reverts to a weak current 5. TEST CONDITIONSI nput x VCC to x VCCI nput Rise and Fall Times 50 nsInput Reference x VCC, x VCCO utput Reference x VCCO utput LoadCurrent Source: IL = 3 mA (VCC V); IL = 1 mA (VCC < V); CL = 100 pFTable 6. CHARACTERISTICS (Note 7)(VCC = V to V, TA = 40 C to +85 C and VCC = V to V, TA = 40 C to +125 C, unless otherwise specified.)SymbolParameterStandardVCC = V VFastVCC = V VFast PlusVCC = V VTA = 405C to +855 CUnitsMinMaxMinMaxMinMaxFSCLC lock Frequency1004001,000kHztHD:STASTART Condition Hold Period of SCL Period of SCL :STASTART Condition Setup :DATData In Hold Time000mstSU:DATData In Setup Time25010050nstR (Note 8)SDA and SCL Rise Time1,000300100nstF (Note 8)SDA and SCL Fall Time300300100nstSU:STOSTOP Condition Setup Free Time BetweenSTOP and Low to Data Out Out Hold Time505050nsTi (Note 8)Noise Pulse Filtered at SCLand SDA Inputs505050nstSU:WPWP Setup Time000mstHD.

7 WPWP Hold Cycle Time555mstPU(Notes 8, 9)Power-up to Ready Test conditions according to Test Conditions Tested initially and after a design or process change that affects this tPU is the delay between the time VCC is stable and the device is ready to accept Reset (POR)The device will power up into Standby mode after VCCexceeds the POR trigger level and will power down intoReset mode when VCC drops below the POR trigger bi directional POR behavior protects the deviceagainst brown out failure, following a temporary loss DescriptionSCL: The Serial Clock input pin accepts the Serial Clocksignal generated by the : The Serial Data I/O pin receives input data andtransmits data stored in EEPROM . In transmit mode, this pinis open drain.

8 Data is acquired on the positive edge, and isdelivered on the negative edge of , A1 and A2: The Address pins accept the device pins have on chip pull down : The Write Protect input pin inhibits all writeoperations, when pulled HIGH. This pin has an on chippull down DescriptionThe CAT24C256 supports the Inter Integrated Circuit(I2C) Bus data transmission protocol, which defines a devicethat sends data to the bus as a transmitter and a devicereceiving data as a receiver. Data flow is controlled by aMaster device, which generates the Serial clock and allSTART and STOP conditions. The CAT24C256 acts as aSlave device. Master and Slave alternate as eithertransmitter or receiver.

9 Up to 8 devices may be connected tothe bus as determined by the device address inputs A0, A1,and Bus ProtocolThe I2C bus consists of two wires , SCL and SDA. Thetwo wires are connected to the VCC supply via pull upresistors. Master and Slave devices connect to the 2 wirebus via their respective SCL and SDA pins. The transmittingdevice pulls down the SDA line to transmit a 0 andreleases it to transmit a 1 .Data transfer may be initiated only when the bus is notbusy (see Characteristics).During data transfer, the SDA line must remain stablewhile the SCL line is HIGH. An SDA transition while SCLis HIGH will be interpreted as a START or STOP condition(Figure 2).STARTThe START condition precedes all commands.

10 It consistsof a HIGH to LOW transition on SDA while SCL is START acts as a wake up call to all receivers. Absenta START, a Slave will not respond to STOP condition completes all commands. It consistsof a LOW to HIGH transition on SDA while SCL is STOP starts the internal Write cycle (when following aWrite command) or sends the Slave into standby mode(when following a Read command).Device AddressingThe Master initiates data transfer by creating a START condition on the bus. The Master then broadcasts an 8 bitserial Slave address. The first 4 bits of the Slave address areset to 1010, for normal Read/Write operations (Figure 3).The next 3 bits, A2, A1 and A0, select one of 8 possible Slavedevices. The last bit, R/W, specifies whether a Read (1) orWrite (0) operation is to be processing the Slave address, the Slave respondswith an acknowledge (ACK) by pulling down the SDA lineduring the 9th clock cycle (Figure 4).