FDV301N - Digital FET, N-Channel

1 DATA Semiconductor Components Industries, LLC, 2009 August, 2021 Rev. 81 Publication Order Number: FDV301N /DDigital FET, N-ChannelFDV301N, FDV301N -F169 General DescriptionThis N Channel logic level enhancement mode field effecttransistor is produced using onsemi s proprietary, high cell density,DMOS technology. This very high density process is especiallytailored to minimize on state resistance. This device has beendesigned especially for low voltage applications as a replacement fordigital transistors. Since bias resistors are not required, this oneN channel FET can replace several different Digital transistors, withdifferent bias resistor 25 V, A Continuous, A Peak RDS(on) = 5 W @ VGS = V RDS(on) = 4 W @ VGS = V Very Low Level Gate Drive Requirements Allowing DirectOperation in 3 V Circuits.

2 VGS(th) < V Gate Source Zener for ESD Ruggedness. > 6 kV Human BodyModel Replace Multiple NPN Digital Transistors with One DMOS FET This Device is Pb Free and Halide FreeFigure 1. Inverter ApplicationDSGINGNDVccOUTMARKING DIAGRAMSOT 23 CASE 318 08 DevicePackageShipping ORDERING INFORMATIONFDV301N, FDV301N F169 SOT 23 3(Pb Free, Halide Free)3000 / Tape & Reel For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationBrochure, BRD8011 Designates Space&Y= Binary Calendar YearCoding Scheme301= Specific Device Code&G= Date CodeDGSFDV301N, FDV301N MAXIMUM RATINGS TA = 25 C unless otherwise , VCCD rain Source Voltage, Power Supply Voltage25 VVGSS, VIGate Source Voltage, VIN8 VID, IODrain/Output Current Power , TSTGO perating and Storage Temperature Range 55 to 150 CESDE lectrostatic Discharge Rating MIL STD 883D Human Body Model(100 pF/1500 W)

3 Exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be CHARACTERISTICS TA = 25 C unless otherwise JAThermal Resistance, Junction to Ambient357 C/WINVERTER ELECTRICAL CHARACTERISTICS TA = 25 C unless otherwise ConditionsMinTypMaxUnitIO(off)Zero Input Voltage Output CurrentVCC = 20 V, VI = 0 V 1mAVI(off)Input VoltageVCC = 5 V, IO = 10 mA (on)VO = V, IO = A1 RO(on)Output to Ground ResistanceVI = V, IO = A 45 WProduct parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.

4 Productperformance may not be indicated by the Electrical Characteristics if operated under different CHARACTERISTICS TA = 25 C unless otherwise noted. SymbolParameterTest ConditionsMinTypMaxUnitOFF CHARACTERISTICSBVDSSD rain Source Breakdown VoltageVGS = 0 V, ID = 250 mA25 VDBVDSS/DTJB reakdown Voltage Temp. CoefficientID = 250 mA, Referenced to 25 C 25 mV/ CIDSSZero Gate Voltage Drain CurrentVDS = 20 V, VGS = 0 V 1mAVDS = 20 V, VGS = 0 V, TJ = 55 C 10 IGSSGate Body Leakage CurrentVGS = 8 V, VDS = 0 V 100nAON CHARACTERISTICSDVGS(th)/DTJGate Threshold Voltage = 250 mA, Referenced to 25 C mV/ CVGS(th)Gate Threshold VoltageVDS = VGS, ID = 250 (on)Static Drain Source On ResistanceVGS = V, ID = A = V, ID = A, TJ = 125 C = V, ID = A (on)On State Drain CurrentVGS = V, VDS = 5 AgFSForward TransconductanceVDS = 5 V, ID = A SFDV301N, FDV301N CHARACTERISTICS TA = 25 C unless otherwise noted.

5 (continued)SymbolUnitMaxTypMinTest ConditionsParameterDYNAMIC CHARACTERISTICSCissInput CapacitanceVDS = 10 V, VGS = 0 V, f = MHz pFCossOutput Capacitance 6 CrssReverse Transfer Capacitance SWITCHING CHARACTERISTICS (Note 1)tD(on)Turn On Delay TimeVDD = 6 V, ID = A, VGS = V,RGEN = 50 W On Rise Time 615tD(off)Turn Off Delay Time Off Fall Time Gate ChargeVDS = 5 V, ID = A, VGS = V Source Charge QgdGate Drain Charge DRAIN SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGSISM aximum Continuous Drain Source Diode Forward Current Source Diode Forward VoltageVGS = 0 V, IS = A (Note 1) parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted.

6 Productperformance may not be indicated by the Electrical Characteristics if operated under different Pulse Test: Pulse Width 300 ms, Duty Cycle CHARACTERISTICSF igure 2. On Region CharacteristicsFigure 3. On Resistance Variation with DrainCurrent and Gate , Drain Current (A)RDS(on), Normalized Drain SourceOn ResistanceVDS, Drain Source Voltage (V)ID, Drain Source Current (A)VGS = VVGS = , FDV301N PERFORMANCE CHARACTERISTICS (continued)Figure 4. On Resistance Variation with TemperatureFigure 5. On Resistance Variation withGate To Source Voltage 50 , Gate to Source Voltage (V)RDS(on), On Resistance (W)TJ, Junction Temperature (5C)RDS(on), Normalized Drain SourceOn = AVGS = = A125 C25 C3 Figure 6.

7 Transfer CharacteristicsFigure 7. Body Diode Forward Voltage Variationwith Source Current and , Body Diode Forward Voltage (V)IS, Reverse Drain Current (A)VGS, Gate to Source Voltage (V)ID, Drain Current (A)VDS = = 55 C25 C125 = 0 VTJ = 125 C25 C 55 CFigure 8. Gate Charge CharacteristicsFigure 9. Capacitance , Drain to Source Voltage (V)Capacitance (pF)Qg, Gate Charge (nC)VGS, Gate Source Voltage (V) = AVDS = 5 V10 V15 V3025f = 1 MHzVGS = 0 VCissCossCrssFDV301N, FDV301N PERFORMANCE CHARACTERISTICS (continued)Figure 10. Maximum Safe Operating AreaFigure 11. Single Pulse Maximum Power Pulse Time (s)Power (W)VDS, Drain Source Voltage (V)ID, Drain Current (A) (on) LimitVGS = VSingle PulseRqJA = 357 C/WTA = 25 C1 ms100 ms1 s10 sDCSingle PulseRqJA = 357 C/WTA = 25 CFigure 12.

8 Transient Thermal Response , Time (s)r(t), Normalized Effective TransientThermal = PulseRqJA (t) = r(t) * RqJARqJA = 357 C/WTJ TA = P * RqJA (t)Duty Cycle, D = t1/t2P(pk)t1t2 SOT 23 (TO 236)CASE 318 08 ISSUE ASDATE 30 JAN 2018 SCALE 4:1DA13121 XXXMGGXXX = Specific Device CodeM= Date CodeG= Pb Free Package*This information is generic. Please refer todevice data sheet for actual part Free indicator, G or microdot G ,may or may not be DIAGRAM*NOTES:1. DIMENSIONING AND TOLERANCING PER ASME , CONTROLLING DIMENSION: MAXIMUM LEAD THICKNESS INCLUDES LEAD LEAD THICKNESS IS THE MINIMUM THICKNESS OFTHE BASE DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,PROTRUSIONS, OR GATE FOOTPRINTVIEW VIEW 22:PIN 1.

9 RETURN2. OUTPUT3. INPUTSTYLE 6:PIN 1. BASE2. EMITTER3. COLLECTORSTYLE 7:PIN 1. EMITTER2. BASE3. COLLECTORSTYLE 8:PIN 1. ANODE2. NO CONNECTION3. CATHODESTYLE 9:PIN 1. ANODE2. ANODE3. CATHODESTYLE 10:PIN 1. DRAIN2. SOURCE3. GATESTYLE 11:PIN 1. ANODE2. CATHODE3. CATHODE ANODESTYLE 12:PIN 1. CATHODE2. CATHODE3. ANODESTYLE 13:PIN 1. SOURCE2. DRAIN3. GATESTYLE 14:PIN 1. CATHODE2. GATE3. ANODESTYLE 15:PIN 1. GATE2. CATHODE3. ANODESTYLE 16:PIN 1. ANODE2. CATHODE3. CATHODESTYLE 17:PIN 1. NO CONNECTION2. ANODE3. CATHODESTYLE 18:PIN 1. NO CONNECTION2. CATHODE3. ANODESTYLE 19:PIN 1.

10 CATHODE2. ANODE3. CATHODE ANODESTYLE 23:PIN 1. ANODE2. ANODE3. CATHODESTYLE 20:PIN 1. CATHODE2. ANODE3. GATESTYLE 21:PIN 1. GATE2. SOURCE3. DRAINSTYLE 1 THRU 5:CANCELLEDSTYLE 24:PIN 1. GATE 2. DRAIN 3. SOURCESTYLE 25:PIN 1. ANODE 2. CATHODE 3. GATESTYLE 26:PIN 1. CATHODE 2. ANODE 3. NO CONNECTIONSTYLE 27:PIN 1. CATHODE 2. CATHODE 3. 100 10T T3 XTOP VIEWSIDE VIEWEND : 28:PIN 1. ANODE 2. ANODE 3. ANODEMECHANICAL CASE OUTLINEPACKAGE DIMENSIONSON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other Semiconductor reserves the right to make changes without further notice to any products herein.