MC74HC393 Dual 4−Stage Binary Ripple Counter

1 Semiconductor Components Industries, LLC, 2006 June, 2006 Rev. 71 Publication Order Number: MC74HC393 /DMC74HC393 dual 4 StageBinary Ripple CounterHigh Performance Silicon Gate CMOSThe MC54/74HC393 is identical in pinout to the LS393. The deviceinputs are compatible with standard CMOS outputs; with pullupresistors, they are compatible with LSTTL device consists of two independent 4 bit Binary Ripple counterswith parallel outputs from each Counter stage . A 256 Counter can beobtained by cascading the two Binary flip flops are triggered by high to low transitions of theclock input. Reset for the counters is asynchronous and active changes of the Q outputs do not occur simultaneously because ofinternal Ripple delays. Therefore, decoded output signals are subject todecoding spikes and should not be used as clocks or as strobes exceptwhen gated with the Clock of the HC393.

2 Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC StandardNo. 7A Chip Complexity: 236 FETs or 59 Equivalent GatesLOGIC DIAGRAMQ1Q2Q3Q4 CLOCKRESET1, 132, 123, 114, 105, 96, 8 PIN 14 = VCCPIN 7 = SUFFIXSOIC PACKAGECASE 751A 03N SUFFIXPLASTIC PACKAGECASE 646 06 ORDERING INFORMATIONMC54 HCXXXJMC74 HCXXXNMC74 HCXXXDC eramicPlasticSOIC114114J SUFFIXCERAMIC PACKAGECASE 632 08114 PIN ASSIGNMENT1112131489105432176Q2bQ1bRESET bCLOCK bVCCQ4bQ3bQ2aQ1aRESET aCLOCK aGNDQ3aQ4aFUNCTION TABLEI nputsClockResetOutputsXH LHLNo ChangeLLNo ChangeLNo ChangeLAdvance toNext StateMC74HC393 MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) to + V Vin DC Input Voltage (Referenced to GND)

3 To VCC + V Vout DC Output Voltage (Referenced to GND) to VCC + V Iin DC Input Current, per Pin 20 mA Iout DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 50 mA PD Power Dissipation in Still Air,Plastic or Ceramic DIP SOIC Package 750500 mW Tstg Storage Temperature 65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds(Plastic or SOIC DIP)(Ceramic DIP) 260300 _C*Maximum Ratings are those values beyond which damage to the device may occur.

4 Functional operation should be restricted to the Recommended Operating Conditions. Derating Plastic DIP: 10 mW/_C from 65_ to 125_CCeramic DIP: 10 mW/_C from 100_ to 125_CSOIC Package: 7 mW/_C from 65_ to 125_CFor high frequency or heavy load considerations, see Chapter 2 of the Motorola High Speed CMOS Data Book (DL129/D).RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) V Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types 55 + 125 _C tr, tf Input Rise and Fall TimeVCC = V(Figure 1)VCC = VVCC = V 000 1000500400 nsDC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

5 Symbol Parameter Test Conditions VCCV Guaranteed Limit Unit 55 to25_C v 85_C v 125_C VIH Minimum High Level InputVoltage Vout = V or VCC V|Iout| v 20 A V VIL Maximum Low Level InputVoltage Vout = V or VCC V|Iout| v 20 A V VOH Minimum High Level OutputVoltage Vin = VIH or VIL|Iout| v 20 A V Vin = VIH or VIL|Iout| v mA|Iout| v mA VOL Maximum Low Level OutputVoltage Vin = VIH or VIL|Iout| v 20 A V Vin = VIH or VIL|Iout| v mA|Iout| v mA Iin Maximum Input Leakage Current Vin = VCC or GND A ICC Maximum Quiescent SupplyCurrent (per Package) Vin = VCC or GNDIout = 0 A 8 80 160 ANOTE.

6 Information on typical parametric values can be found in Chapter 2 of the Motorola High Speed CMOS Data Book (DL129/D).This device contains protectioncircuitry to guard against damagedue to high static voltages or electricfields. However, precautions mustbe taken to avoid applications of anyvoltage higher than maximum ratedvoltages to this high impedance cir-cuit. For proper operation, Vin andVout should be constrained to therange GND v (Vin or Vout) v inputs must always betied to an appropriate logic voltagelevel ( , either GND or VCC).Unused outputs must be left ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) Symbol Parameter VCCV Guaranteed Limit Unit 55 to25_C v 85_C v 125_C fmax Maximum Clock Frequency (50% Duty Cycle)(Figures 1 and 3) MHz tPLH,tPHL Maximum Propagation Delay, Clock to Q1(Figures 1 and 3) 1202420 1503026 1803631 ns tPLH,tPHL Maximum Propagation Delay, Clock to Q2(Figures 1 and 3)

7 1903832 2404841 2855748 ns tPLH,tPHL Maximum Propagation Delay, Clock to Q3(Figures 1 and 3) 2404841 3006051 3607261 ns tPLH,tPHL Maximum Propagation Delay, Clock to Q4(Figures 1 and 3) 2905849 3657362 4358774 ns tPHL Maximum Propagation Delay, Reset to any Q(Figures 2 and 3) 1653328 2054135 2505043 ns tTLH,tTHL Maximum Output Transition Time, Any Output(Figures 1 and 3) 751513 951916 1102219 ns Cin Maximum Input Capacitance 10 10 10 pFNOTES:1.

8 For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High Speed CMOS Data Book (DL129/D).2. Information on typical parametric values can be found in Chapter 2 of the Motorola High Speed CMOS Data Book (DL129/D).CPDP ower Dissipation Capacitance (Per Counter )*Typical @ 25 C, VCC = VpF40* Used to determine the no load dynamic power consumption: PD = CPD VCC2f + ICC VCC. For load considerations, see Chapter 2 of theMotorola High Speed CMOS Data Book (DL129/D).TIMING REQUIREMENTS (Input tr = tf = 6 ns) Symbol Parameter VCCV Guaranteed Limit Unit 55 to25_C v 85_C v 125_C trec Minimum Recovery Time, Reset Inactive to Clock(Figure 2) 50109 651311 751513 ns tw Minimum Pulse Width, Clock(Figure 1) 801614 1002017 1202420 ns tw Minimum Pulse Width, Reset(Figure 2)

9 1252521 1553126 1903832 ns tr, tf Maximum Input Rise and Fall Times(Figure 1) 1000500400 1000500400 1000500400 nsNOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High Speed CMOS Data Book (DL129/D). MC74HC393 DESCRIPTIONSINPUTSC lock (Pins 1, 13)Clock input. The internal flip flops are toggled and thecounter state advances on high to low transitions of theclock INPUTSR eset (Pins 2, 12)Active high, asynchronous reset. A separate reset isprovided for each Counter . A high at the Reset inputprevents counting and forces all four outputs , Q2, Q3, Q4 (Pins 3, 4, 5, 6, 8, 9, 10, 11)Parallel Binary outputs Q4 is the most significant WAVEFORMStPHLVCCGNDVCCGND50%50%50%trecCL OCKQRESETF igure 1.

10 Figure 2. Figure 3. Test CircuitQ1Q2Q3Q4 CLOCKRESET1, 132, 123, 114, 105, 96, 8 EXPANDED LOGIC DIAGRAM*Includes all probe and jig capacitanceCL*TESTPOINTDEVICEUNDERTESTOU TPUTCLOCKQ90%90%50%10%tftrVCCGNDtw1/fmax tPLHtPHL90%50%10%tTLHtTHLCDQtwQCDQQCDQQC DQQMC74HC393 DIAGRAMCOUNT SEQUENCEC ountOutputsQ4Q3Q2Q10 LLLL1 LLLH2 LLHL3 LLHH4 LHLL5 LHLH6 LHHL7 LHHH8 HLLL9 HLLH10 HLHL11 HLHH12 HHLL13 HHLH14 HHHL15 HHHHMC74HC393 DIMENSIONSJ SUFFIXCERAMIC DIP PACKAGECASE 632 08 ISSUE BSCNOTES:1. DIMENSIONING AND TOLERANCING PER , CONTROLLING DIMENSION: DIMENSION L TO CENTER OF LEAD WHENFORMED DIMESNION F MAY NARROW TO ( )WHERE THE LEAD ENTERS THE ( ) ( )TBMSJ 14 PLD 14 PLN SUFFIXPLASTIC DIP PACKAGECASE 646 06 ISSUE LNOTES:1. LEADS WITHIN ( ) RADIUS OF TRUEPOSITION AT SEATING PLANE AT MAXIMUMMATERIAL DIMENSION L TO CENTER OF LEADS WHENFORMED DIMENSION B DOES NOT INCLUDE ROUNDED CORNERS MINMAXMIN BSCM0 10 0 10 SUFFIXPLASTIC SOIC PACKAGECASE 751A 03 ISSUE BSCNOTES:1.