MC74HC4060A - 14-Stage Binary Ripple Counter …

1 Semiconductor Components Industries, LLC, 2016 June, 2016 Rev. 101 Publication Order Number: MC74HC4060A /DMC74HC4060A14- stage Binary RippleCounter With OscillatorHigh Performance Silicon Gate CMOSThe MC74HC4060A is identical in pinout to the standard CMOSMC14060B. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with device consists of 14 master slave flip flops and an oscillatorwith a frequency that is controlled either by a crystal or by an RCcircuit connected externally. The output of each flip flop feeds thenext and the frequency at each output is half of that of the precedingone. The state of the Counter advances on the negative going edge ofthe Osc In. The active high Reset is asynchronous and disables theoscillator to allow very low power consumption during stand changes of the Q outputs do not occur simultaneously becauseof internal Ripple delays.

2 Therefore, decoded output signals are subjectto decoding spikes and may have to be gated with Osc Out 2 of Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: to V Low Input Current: 1 mA High Noise Immunity Characteristic of CMOS Devices In Compliance With JEDEC Standard No. 7A Requirements Chip Complexity: 390 FETs or Equivalent Gates NLV Prefix for Automotive and Other Applications RequiringUnique Site and Control Change Requirements; AEC Q100 Qualified and PPAP Capable These Devices are Pb Free, Halogen Free/BFR Free and are RoHSCompliantLOGIC DIAGRAMQ47Q55Q64Q76Q814Q913Q1015Q121Q132 Q143 Osc In11 Reset12 Pin 16 = VCCPin 8 = GNDOsc Out 1 Osc Out detailed ordering and shipping information in the packagedimensions section on page 4 of this data INFORMATIONMARKING DIAGRAMSSOIC 16D SUFFIXCASE 751 BTSSOP 16DT SUFFIXCASE 948F116HC4060 AGAWLYWWHC4060 AALYWGG116A= Assembly LocationL, WL= Wafer LotY, YY= YearW, WW= Work WeekG or G= Pb Free Package(Note.)

3 Microdot may be in either location)FUNCTION TABLEC lockResetOutput StateXLLHNo ChangeAdvance to Next StateAll Outputs Are LowSOIC 16 TSSOP 16 PIN ASSIGNMENT16 Lead Package (Top View)151614131211102134567 VCC98Q10Q8Q9 Reset Osc InOscOut 1 OscOut RATINGSS ymbolParameterValueUnitVCCDC Supply Voltage (Referenced to GND) to + Input Voltage (Referenced to GND) to VCC + Output Voltage (Referenced to GND) to VCC + Input Current, per Pin 20mAIoutDC Output Current, per Pin 25mAICCDC Supply Current, VCC and GND Pins 50mAPDP ower Dissipation in Still Air,SOIC Package TSSOP Package 500450mWTstgStorage Temperature Range 65 to + 150_CTLLead Temperature, 1 mm from Case for 10 SecondsSOIC or TSSOP Package260_CStresses exceeding those listed in the Maximum Ratings table may damage the device. If any ofthese limits are exceeded, device functionality should not be assumed, damage may occur andreliability may be affected.

4 Derating: SOIC Package: 7 mW/_C from 65_ to 125_CTSSOP Package: mW/_C from 65_ to 125_CRECOMMENDED OPERATING CONDITIONSS ymbolParameterMinMaxUnitVCCDC Supply Voltage (Referenced to GND) * , VoutDC Input Voltage, Output Voltage (Referenced to GND)0 VCCVTAO perating Temperature Range, All Package Types 55+125_Ctr, tfInput Rise/Fall TimeVCC = V(Figure 1)VCC = VVCC = V0001000500400nsFunctional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyondthe Recommended Operating Ranges limits may affect device reliability.*The oscillator is guaranteed to function at V minimum. However, parametrics are tested V by driving Pin 11 with an external clock CHARACTERISTICS (Voltages Referenced to GND) SymbolParameterConditionVCCVG uaranteed LimitUnit 55 to 25 C 85 C 125 CVIHM inimum High Level Input VoltageVout = or VCC |Iout| Low Level Input VoltageVout = or VCC |Iout| High Level Output Voltage(Q4 Q10, Q12 Q14)Vin = VIH or VIL|Iout| =VIH or VIL|Iout| |Iout| |Iout| Low Level Output Voltage(Q4 Q10, Q12 Q14)Vin = VIH or VIL|Iout| = VIH or VIL|Iout| |Iout| |Iout| device contains protectioncircuitry to guard against damagedue to high static voltages or electricfields.

5 However, precautions mustbe taken to avoid applications of anyvoltage higher than maximum ratedvoltages to this high impedance cir-cuit. For proper operation, Vin andVout should be constrained to therange GND v (Vin or Vout) v inputs must always betied to an appropriate logic voltagelevel ( , either GND or VCC).Unused outputs must be left CHARACTERISTICS (Voltages Referenced to GND) (continued)SymbolUnitGuaranteed LimitVCCVC onditionParameterSymbolUnit 125 C 85 C 55 to 25 CVCCVC onditionParameterVOHM inimum High Level Output Voltage(Osc Out 1, Osc Out 2)Vin = VCC or GND|Iout| =VCC or GND|Iout| |Iout| |Iout| Low Level Output Voltage(Osc Out 1, Osc Out 2)Vin = VCC or GND|Iout| =VCC or GND|Iout| |Iout| |Iout| Input Leakage CurrentVin = VCC or Quiescent SupplyCurrent (per Package)Vin = VCC or GNDIout = CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)SymbolParameterVCCVG uaranteed LimitUnit 55 to 25 C 85 C 125 CfmaxMaximum Clock Frequency (50% Duty Cycle)(Figures 1 and 4) ,tPHLM aximum Propagation Delay, Osc In to Q4*(Figures 1 and 4)

6 ,tPHLM aximum Propagation Delay, Osc In to Q14*(Figures 1 and 4) Propagation Delay, Reset to Any Q(Figures 2 and 4) ,tPHLM aximum Propagation Delay, Qn to Qn+1(Figures 3 and 4) CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns) continuedSymbolParameterVCCVG uaranteed LimitUnit 55 to 25 C 85 C 125 CtTLH,tTHLM aximum Output Transition Time, Any Output(Figures 1 and 4) Input Capacitance101010pF* For TA = 25 C and CL = 50 pF, typical propagation delay from Clock to other Q outputs may be calculated with the following equations:VCC = V: tP = [ + (n 1)] nsVCC = V: tP = [ + (n 1)] nsVCC = V: tP = [ + (n 1)] nsVCC = V: tP = [ + 12 (n 1)] nsCPDP ower Dissipation Capacitance (Per Package)*Typical @ 25 C, VCC = VpF35* Used to determine the no load dynamic power consumption: PD = CPD VCC2f + ICC REQUIREMENTS (Input tr = tf = 6 ns)SymbolParameterVCCVG uaranteed LimitUnit 55 to 25 C 85 C 125 CtrecMinimum Recovery Time, Reset Inactive to Clock(Figure 2) Pulse Width, Clock(Figure 1) Pulse Width, Reset(Figure 2) , tfMaximum Input Rise and Fall Times(Figure 1) INFORMATIOND evicePackageShipping MC74HC4060 ADGSOIC 16(Pb Free)48 Units / RailMC74HC4060 ADR2 GSOIC 16(Pb Free)2500 Units / ReelNLV74HC4060 ADR2G*SOIC 16(Pb Free)2500 Units / ReelMC74HC4060 ADTGTSSOP 16(Pb Free)96 Units / RailMC74HC4060 ADTR2 GTSSOP 16(Pb Free)2500 Units / ReelNLVHC4060 ADTR2G*TSSOP 16(Pb Free)2500 Units / Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011/D.

7 *NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC Q100 Qualified and DESCRIPTIONSINPUTSOsc In (Pin 11)Negative edge triggering clock input. A high to lowtransition on this input advances the state of the Counter . OscIn may be driven by an external clock (Pin 12)Active high reset. A high level applied to this inputasynchronously resets the Counter to its zero state (forcingall Q outputs low) and disables the Q10, Q12 Q14 (Pins 7, 5, 4, 6, 13, 15, 1, 2, 3)Active high outputs. Each Qn output divides the Clockinput frequency by 2N. The user should note the Q1, Q2, Q3and Q11 are not available as Out 1, Osc Out 2 (Pins 9, 10)Oscillator outputs. These pins are used in conjunctionwith Osc In and the external components to form anoscillator.

8 When Osc In is being driven with an externalclock source, Osc Out 1 and Osc Out 2 must be left opencircuited. With the crystal oscillator configuration inFigure 6, Osc Out 2 must be left open WAVEFORMS twtfOsc InQVCCGND90%50%10%trtw90%50%10%tPHL1/fMA XtPLHtTLHtTHLR esetVCCGNDtPHL50%Figure 1. Figure 2. QVCCGND50%Osc In50%trec50%QnVCCGND50%Qn+1CL**Includes all probe and jig capacitanceTESTPOINTDEVICEUNDERTESTOUTPU TF igure 3. Figure 4. Test 5. Expanded Logic DiagramCCROsc Out 29 QQCCRQQCCQQCCQQCCQQCCQQ47Q55Q121Q132Q143 Q6 = Pin 4Q7 = Pin 6Q8 = Pin 14Q9 = Pin 13Q10 = Pin 15 VCC = Pin 16 GND = Pin 8 Osc Out 110 Osc In11 Reset12 Figure 6. Oscillator Circuit Using RC ConfigurationReset12 Osc In11 Osc Out 110 Osc Out 29 RtcCtcRSFor VCC > RS > 2 Rtc400Hz f 400 Khz:f[ RtcCtc (f in Hz, Rtc in ohms, Ctc in farads)The formula may vary for other 7.]

9 Pierce Crystal Oscillator CircuitReset12 Osc In11 Osc Out 1109 Osc Out 1. CRYSTAL OSCILLATOR AMPLIFIER SPECIFICATIONS (TA = 25 C; Input = Pin 11, Output = Pin 10)TypePositive Reactance (Pierce)Input Resistance, Rin60MW MinimumOutput Impedance, Zout ( Supply)200W (See Text)Input Capacitance, Cin5pF TypicalOutput Capacitance, Cout7pF TypicalSeries Capacitance, Ca5pF TypicalOpen Loop Voltage Gain with Output at Full Swing, 3 Vdc Supply4 Vdc Supply5 Vdc Supply6 Vdc Expected Expected Expected Expected MinimumPIERCE CRYSTAL OSCILLATOR DESIGNF igure 8. Equivalent Crystal NetworksRSLSCSReXe212121 COValue are supplied by crystal manufacturer (parallel resonant crystal).Figure 9. Series Equivalent Crystal LoadFigure 10. Parasitic Capacitances of the AmplifierZload-jXCo-jXC2R-jXC-jXCsjXLsRS RloadXloadNOTE: C = C1 + Cin and R = R1 + Rout.

10 Co is considered as part ofthe load. Ca and Rf typically have minimal effect below are listed in Table PROCEDURESThe following procedure applies for oscillators operating below 2 MHz where Z is a resistor R1. Above 2 MHz, additionalimpedance elements should be considered: Cout and Ca of the amp, feedback resistor Rf, and amplifier phase shift error from180 1: Calculate the equivalent series circuit of the crystal at the frequency of +*jXCo(Rs)jXLs*jXCs)*jXCo)Rs)jXLs*jXCs+R e)jXeReactance jXe should be positive, indicating that the crystal is operating as an inductive reactance at the oscillation maximum Rs for the crystal should be used in the 2: Determine , the attenuation, of the feedback network. For a closed-loop gain of 2,A = 2, = 2/A where A isthe gain of the HC4060A 3: Determine the manufacturer s loading capacitance.