Micro Structure Observation and Reliability …

1 73 Orii et al.: Micro Structure Obser vation and Reliability behavior (1/14)[Technical Paper] Micro Structure Obser vation and Reliability behavior of Peripheral flip chip Interconnections with Solder-Capped Cu Pillar BumpsYasumitsu Orii*, Kazushige Toriyama*, Sayuri Kohara*, Hirokazu Noma*, Keishi Okamoto*, Daisuke Toyoshima**, and Keisuke Uenishi**IBM Research Tokyo, 1623-14, Shimotsuruma, Yamato-city, Kanagawa-ken 242-8502, Japan**Osaka University, 2-1, Yamadaoka, Suita, Osaka 565-0871, Japan(Received September 1, 2011; accepted November 10, 2011)AbstractPoP (Package on Package) structures have been used widely in digital consumer electronics products such as digital still cameras and mobile phones.

2 However, the final stack height from the top to the bottom package for these structures is higher than that of the current stacked die packages. To reduce the height of the package, a flip chip technology is used. Since the logic chips of mobile applications use a pad pitch of less than 80 m or less, an ultra-fine-pitch flip chip intercon-nection technique is required. The C4 (Controlled Collapse chip Connection) flip chip technology is widely used in area array flip chip packages. The C4 was named after the four initial characters which are C of Controlled Collapse chip Connection. The collapse of the molten solder is controlled by the individual opening of solder resist on each pad on the substrate so that the chip can be connected onto the substrate.

3 However, C4 is not suitable in the ultra-fine-pitch flip chips because the such a individual opening which is suitable for the ultra-fine-pitch cannot be made on the substraete. Instead of the C4 flip chip technology, the new interconnection technique was developed using the solder capped Cu pillar bumps. It is ver y easy to control the space between the die and the substrate by adjusting the Cu pillar height even when a large slit window opening exists on a group of pads on the substrate. Since the collapse control of the solder bumps is not necessar y, we call the process C2 ( chip Connection). The C2 was named after the two initial characters which are C of chip Connection.

4 The solder capped Cu pillar bumps are connected to Cu substrate pads, which are a surface treated with OSP (Organic Solder Preser vative), by reflow with no-clean processes. This technology creates the SMT (Surface Mount Technology)/ flip chip hybrid assembly for SoP (System on Package) use. We have produced 50 m pitch intercon-nections and obser ved the Micro Structure and tested their Reliability . Some voids in the solder joint were obser ved after the reflow process. The results of warpage measurements and FEM (Finite Element Method) analyses suggest that these voids are the shrinkage voids caused by the wide temperature range of the solder liquid phase and the substrate warpage.

5 Since they are not the stress induced voids, they didn t affect the Reliability test. The increase in interconnection resis-tance during the Reliability test was compared between the C2 interconnection and Au stud-solder interconnection. Since the resistance increase of the C2 interconnection is much smaller than that for the Au stud-solder interconnection, it is clear that the C2 flip chip technology provides robust solder connections at low cost. Also the C2 Structure with a low-k device was evaluated and no failures were obser ved at 1,500 cycles in the TC (Thermal Cycle) test. In addition to the fine-pitch interconnections, a die thickness of 70 m is required to reduce the final stack height.

6 The Reliability perfor-mance of the C2 flip chip with the die thicknesses 20 m, 70 m and 150 m was also discussed using a PEG (Post-Encapsulation Grinding) method in which the die is ground to less than 70 m after joining and underfilling. Finally the electromigration tests were performed on the 80 m pitch C2 interconnection. The tests showed that the solder capped Cu pillar Structure has high endurance against electromigration and no failure data was recorded up to 1,000 hrs with several electromigration conditions regardless the direction of electron : flip chip , Cu Pillar, Shrinkage, Thin Die, Electromigration, Low-k, IMC74 Transactions of The Japan Institute of Electronics Packaging Vol.

7 4, No. 1, 20111. IntroductionPoP[1] is an emerging technology intended to replace the wire-bonding stacked die technology.[2] It has been widely used in digital consumer electronics products such as digital still cameras and mobile phones. One of the dis-advantages of PoP is that the final stack-up-height, from the top to the bottom of the package, is greater than that for the stacked die packages. For this reason, flip - chip -PoP, in which the flip chip technology is used for the bot-tom package, became popular. Since the die of the bottom packages in PoP is designed for the wire-bonding technol-ogy, the I/O pads are located on the peripher y of the die with a fine-pitch, such as 80 m or less.

8 A number of flip chip interconnection methods are available in the industr y, but only few technologies are dedicated for ultra-fine-pitch flip chips on organic substrates. The technology widely used in Japan for digital still cameras and mobile phones is Au stud-solder interconnections.[3] However, this technol-ogy is high-cost, low-throughput and not SMT compatible. There are three known drawbacks for this technology. One of the drawbacks being the need for the pre-formed Sn-Ag solder on the Cu pads of the substrates. This increases the manufacturing costs and results in a large variation in solder heights, since the solder heights are determined by the Cu pad widths.

9 The technology has a long processing time due to the thermal compression bonding performed for each die. The bonding also requires an expensive equipment. The other drawback is the narrow process margin due to the creation of compli-cated IMC (Intermetallic Compounds) which increases the interconnection resistance. These drawbacks inhibit the expanded use of the flip chip infrastructures. A new technology is needed to extend the standard C4 technol-ogy that was introduced by IBM in the early 1960s for its SLC (Solid Logic Technology). The C4 technology is a high-throughput flip chip technology and is still widely used for CPUs in PCs and games.

10 However, this technol-ogy is normally used for the systems having bump pitch of greater than 150 m and is not suited for the fine-pitch applications. In the fine-pitch systems, the space between the die and the substrate becomes narrow which can cause solder bridges in the C4 technology because of the collapsing of the bumps. The underfill insertion is also dif-ficult for narrow spaces. Figure 1 shows a solder-resist opening for flip chip pads. The individual window design helps control the collapse of the solder bumps during reflow, but this design cannot be used for fine-pitch sys-tems because of the alignment limitation in organic sub-strate manufacturing.