NUP4114 Series ESD Protection Diode - ON Semiconductor

1 Semiconductor Components Industries, LLC, 2014 July, 2018 Rev. 61 Publication Order Number: NUP4114 /DNUP4114 SeriesESD Protection DiodeLow Clamping VoltageThe NUP4114 ESD Protection Diode array is designed to protecthigh speed data lines from ESD. Ultra low capacitance and high levelof ESD Protection make these devices well suited for use in USB speed Low Clamping Voltage Low Capacitance (< pF Typical, I/O to GND) Low Leakage Response Time is Typically < ns IEC61000 4 2 Level 4 ESD Protection SZ Prefix for Automotive and Other Applications Requiring UniqueSite and Control Change Requirements; AEC Q101 Qualified andPPAP Capable These Devices are Pb Free, Halogen Free/BFR Free and are RoHSCompliantTypical Applications LVDS USB High Speed Data Line and Power Line Protection Digital Video Interface (DVI) and HDMI Gigabit Ethernet Monitors and Flat Panel Displays Notebook ComputersMAXIMUM RATINGS (TJ = 25 C unless otherwise noted)RatingSymbolValueUnitOperating Junction Temperature RangeTJ 40 to +125 CStorage Temperature RangeTstg 55 to +150 CLead Solder Temperature Maximum (10 Seconds)

2 TL260 CIEC 61000 4 2 ContactIEC 61000 4 2 AirISO 10605 330 pF / 330 W ContactISO 10605 330 pF / 2 kW ContactISO 10605 150 pF / 2 kW ContactESD 8 15 10 21 30kVStresses exceeding those listed in the Maximum Ratings table may damage thedevice. If any of these limits are exceeded, device functionality should not beassumed, damage may occur and reliability may be Application Note AND8308/D for further description of survivability MGGXXX = Specific Device CodeM= Date CodeG= Pb Free Package161SC 88W1 SUFFIXCASE 419B(Note: Microdot may be in either location)536214X4 MGG161SC 88W1 SUFFIXCASE 419BP4H MGG16 TSOP 6 CASE 318 GSTYLE 121 SOT 563 CASE 463AP4 MGG116 See detailed ordering and shipping information in the packagedimensions section on page 4 of this data INFORMATIONNUP4114 CHARACTERISTICS(TA = 25 C unless otherwise noted)

3 SymbolParameterIPPM aximum Reverse Peak Pulse CurrentVCClamping Voltage @ IPPVRWMW orking Peak Reverse VoltageIRMaximum Reverse Leakage Current @ VRWMVBRB reakdown Voltage @ ITITTest CurrentIFForward CurrentVFForward Voltage @ IFPpkPeak Power DissipationCCapacitance @ VR = 0 and f = MHz*See Application Note AND8308/D for detailed explanations ofdatasheet DirectionalIPPIFVIIRITVRWMVCVBRVFELECTRI CAL CHARACTERISTICS (TJ = 25 C unless otherwise specified)ParameterSymbolConditionsMinTy pMaxUnitReverse Working VoltageVBRIT = 1 mA, (Note 1) Leakage CurrentIRVRWM = VoltageVCIPP = 1 A (Note 2) = 5 A (Note 3) = 8 A (Note 3) Clamping VoltageVCPer IEC61000 4 2 (Note 4)See Figures 1 & 2 Maximum Peak Pulse CurrentIPP8/20 ms Waveform (Note 3)12 AJunction CapacitanceCJVR = 0 V, f = 1 MHz between I/O Pins and = 0 V, f = 1 MHz between I/O VBR is measured at pulse test current Nonrepetitive current pulse (I/O to GND).

4 3. Nonrepetitive current pulse (Pin 5 to Pin 2)4. For test procedure see Figures 3 and 4 and Application Note AND8307 1. ESD Clamping Voltage ScreenshotPositive 8 kV Contact per IEC61000 4 2 Figure 2. ESD Clamping Voltage ScreenshotNegative 8 kV Contact per IEC61000 4 2 NUP4114 61000 4 2 Volt-age (kV)First PeakCurrent(A)Current at30 ns (A)Current at60 ns (A) 4 2 Waveform100%I @ 30 nsI @ 60 nstP = ns to 1 nsFigure 3. IEC61000 4 2 SpecFigure 4. Diagram of ESD Test Setup50 WCableDeviceUnderTestOscilloscopeESD Gun50 WThe following is taken from Application NoteAND8308/D Interpretation of Datasheet Parametersfor ESD Voltage ClampingFor sensitive circuit elements it is important to limit thevoltage that an IC will be exposed to during an ESD eventto as low a voltage as possible.

5 The ESD clamping voltageis the voltage drop across the ESD Protection Diode duringan ESD event per the IEC61000 4 2 waveform. Since theIEC61000 4 2 was written as a pass/fail spec for largersystems such as cell phones or laptop computers it is notclearly defined in the spec how to specify a clamping voltageat the device level. ON Semiconductor has developed a wayto examine the entire voltage waveform across the ESDprotection Diode over the time domain of an ESD pulse in theform of an oscilloscope screenshot, which can be found onthe datasheets for all ESD Protection diodes. For moreinformation on how ON Semiconductor creates thesescreenshots and how to interpret them please refer toAND8307 5.

6 8/20 ms Pulse Waveform1009080706050403020100020406080t , TIME (ms)% OF PEAK PULSE CURRENTtPtrPULSE WIDTH (tP) IS DEFINEDAS THAT POINT WHERE THEPEAK CURRENT DECAY = 8 msPEAK VALUE IRSM @ 8 msHALF VALUE IRSM/2 @ 20 msNUP4114 6. 500 MHz Data PatternORDERING INFORMATIOND eviceMarkingPackageShipping NUP4114 UCLW1T2GX2SC 88(Pb Free)3000 / Tape & ReelSZNUP4114 UCLW1T2GX2 NUP4114 UCW1T2GX4 NUP4114 UPXV6T1GP4 SOT 563(Pb Free)4000 / Tape & ReelNUP4114 UPXV6T2 GNUP4114 HMR6T1GP4 HTSOP 6(Pb Free)3000 / Tape & ReelSZNUP4114 HMR6T1GP4H For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011 INFORMATIONThe new NUP4114 is a low capacitance ESD Diode arraydesigned to protect sensitive electronics such ascommunications systems, computers, and computerperipherals against damage due to ESD events or transientovervoltage conditions.

7 Because of its low capacitance, itcan be used in high speed I/O data lines. The integrateddesign of the NUP4114 offers low capacitance steeringdiodes and an ESD Diode integrated in a single package(TSOP 6). If a transient condition occurs, the steeringdiodes will drive the transient to the positive rail of thepower supply or to ground. This device protects the powerline against overvoltage conditions to avoid damage to thepower supply and any downstream Configuration OptionsThe NUP4114 is able to protect up to four data linesagainst transient overvoltage conditions by driving them toa fixed reference point for clamping purposes. The steeringdiodes will be forward biased whenever the voltage on theprotected line exceeds the reference voltage (Vf orVCC + Vf).

8 The diodes will force the transient current tobypass the sensitive lines are connected at pins 1, 3, 4 and 6. The negativereference is connected at pin 2. This pin must be connecteddirectly to ground by using a ground plane to minimize thePCB s ground inductance. It is very important to reduce thePCB trace lengths as much as possible to minimize 1 Protection of four data lines and the power supply usingVCC as 1I/O 2I/O 3I/O 4 VCC654123 For this configuration, connect pin 5 directly to thepositive supply rail (VCC), the data lines are referenced tothe supply voltage. The internal ESD Diode preventsovervoltage on the supply rail. Biasing of the steering diodesreduces their 2 Protection of four data lines with bias and power supplyisolation kI/O 1I/O 2I/O 3I/O 4654123 The NUP4114 can be isolated from the power supply byconnecting a Series resistor between pin 5 and VCC.

9 A 10 kWresistor is recommended for this application. This willmaintain a bias on the internal ESD and steering diodes,reducing their 3 Protection of four data lines using the internal ESD diodeas 1I/O 2I/O 3I/O 4NC654123In applications lacking a positive supply reference orthose cases in which a fully isolated power supply isrequired, the internal ESD can be used as the reference. Forthese applications, pin 5 is not connected. In thisconfiguration, the steering diodes will conduct whenever thevoltage on the protected line exceeds the working voltage ofthe ESD plus one Diode drop (VC = Vf + VESD).ESD Protection of Power Supply LinesWhen using diodes for data line Protection , referencing toa supply rail provides advantages.

10 Biasing the diodesreduces their capacitance and minimizes signal this topology with discrete devices does havedisadvantages. This configuration is shown below:VCCD1D2 Data LineIESDposIESDnegVF + VCC VFIESDposIESDnegPowerSupplyProtectedDevi ceLooking at the figure above, it can be seen that when apositive ESD condition occurs, Diode D1 will be forwardbiased while Diode D2 will be forward biased when anegative ESD condition occurs. For slower transientconditions, this system may be approximated as follows:For positive pulse conditions:Vc = VCC + VfD1 For negative pulse conditions:Vc = VfD2 ESD events can have rise times on the order of somenumber of nanoseconds.