SG3525A Pulse Width Modulator Control Circuit

1 Semiconductor Components Industries, LLC, 2005 January, 2005 Rev. 51 Publication Order Number: SG3525A /DSG3525 APulse Width ModulatorControl CircuitThe SG3525A Pulse Width Modulator Control Circuit offersimproved performance and lower external parts count whenimplemented for controlling all types of switching power on chip + V reference is trimmed to 1% and the erroramplifier has an input common mode voltage range that includes thereference voltage, thus eliminating the need for external dividerresistors.

2 A sync input to the oscillator enables multiple units to beslaved or a single unit to be synchronized to an external system wide range of deadtime can be programmed by a single resistorconnected between the CT and Discharge pins. This device alsofeatures built in soft start circuitry, requiring only an external timingcapacitor. A shutdown pin controls both the soft start circuitry and theoutput stages, providing instantaneous turn off through the PWM latchwith pulsed shutdown, as well as soft start recycle with longershutdown commands.

3 The under voltage lockout inhibits the outputsand the changing of the soft start capacitor when VCC is belownominal. The output stages are totem pole design capable of sinkingand sourcing in excess of 200 mA. The output stage of the SG3525 Afeatures NOR logic resulting in a low output for an off V to 35 V Operation V Trimmed Reference 100 Hz to 400 kHz Oscillator Range Separate Oscillator Sync Pin Adjustable Deadtime Control Input Undervoltage Lockout Latching PWM to Prevent Multiple Pulses Pulse by Pulse Shutdown Dual Source/Sink Outputs.

4 400 mA Peak Pb Free Packages are Available**For additional information on our Pb Free strategy and soldering details, pleasedownload the ON Semiconductor Soldering and Mounting TechniquesReference Manual, Assembly LocationWL = Wafer LotYY = YearWW = Work Week116 PDIP 16N SUFFIXCASE 648116SG3525 ANAWLYYWWPIN CONNECTIONS12345678910111213141516(Top View)Inv. InputSyncOSC. OutputRTDischargeSoft-StartNoninv. InputCTCompensationShutdownOutput AVCO utput BVCCVrefGround116SG3525 AAWLYYWWSOIC 16 LDW SUFFIXCASE 751 GSee detailed ordering and shipping information in the packagedimensions section on page 2 of this data INFORMATION161 1.

5 Representative Block DiagramNORNOR16151243657912810 ReferenceRegulatorUnder-VoltageLockoutOs cillatorLatchF/FQQ- PWME rrorAmp+-+-To InternalCircuitryVREFVrefVCCG roundOSC OutputSyncRTCTD ischargeCompensationINV. InputNoninv. AVC13 Output A1114 Output BSG3525A Output INFORMATIOND evicePackageShipping SG3525 ANPDIP 1625 Units / RailSG3525 ANGPDIP 16(Pb Free)25 Units / RailSG3525 ADWSOIC 16L47 Units / RailSG3525 ADWGSOIC 16L(Pb Free)47 Units / RailSG3525 ADWR2 SOIC 16L1000 Tape & ReelSG3525 ADWR2 GSOIC 16L(Pb Free)1000 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel PackagingSpecifications Brochure, BRD8011 RATINGSR atingSymbolValueUnitSupply VoltageVCC+40 VdcCollector Supply VoltageVC+40 VdcLogic Inputs to + Inputs to VCCVO utput Current, Source or SinkIO 500mAReference Output CurrentIref50mAOscillator Charging DissipationTA = +25 C (Note 1)TC = +25 C (Note 2)

6 PD10002000mWThermal Resistance, Junction to AirR JA100 C/WThermal Resistance, Junction to CaseR JC60 C/WOperating Junction TemperatureTJ+150 CStorage Temperature RangeTstg 55 to +125 CLead Temperature (Soldering, 10 seconds)TSolder+300 CMaximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limitvalues (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied,damage may occur and reliability may be Derate at 10 mW/ C for ambient temperatures above +50 Derate at 16 mW/ C for case temperatures above +25 OPERATING CONDITIONSC haracteristicsSymbolMinMaxUnitSupply Supply Sink/Source Current(Steady State)(Peak)

7 IO00 100 400mAReference Load CurrentIref020mAOscillator Frequency Timing Oscillator Timing FDeadtime Resistor RangeRD0500 Operating Ambient Temperature RangeTA0+70 CAPPLICATION INFORMATIONS hutdown Options (See Block Diagram, page 2)Since both the compensation and soft start terminals(Pins 9 and 8) have current source pull ups, either canreadily accept a pull down signal which only has to sink amaximum of 100 A to turn off the outputs. This is subjectto the added requirement of discharging whatever externalcapacitance may be attached to these alternate approach is the use of the shutdown circuitryof Pin 10 which has been improved to enhance the availableshutdown options.

8 Activating this Circuit by applying apositive signal on Pin 10 performs two functions: the PWMlatch is immediately set providing the fastest turn off signalto the outputs; and a 150 A current sink begins to dischargethe external soft start capacitor. If the shutdown commandis short, the PWM signal is terminated without significantdischarge of the soft start capacitor, thus, allowing, forexample, a convenient implementation of Pulse by pulsecurrent limiting. Holding Pin 10 high for a longer duration,however, will ultimately discharge this external capacitor,recycling slow turn on upon 10 should not be left floating as noise pickup couldconceivably interrupt normal CHARACTERISTICS (VCC = +20 Vdc, TA = Tlow to Thigh [Note 3], unless otherwise noted.)

9 CharacteristicsSymbolMinTypMaxUnitREFERE NCE SECTIONR eference Output Voltage (TJ = +25 C) Regulation (+ V VCC +35 V)Regline 1020mVLoad Regulation (0 mA IL 20 mA)Regload 2050mVTemperature Stability Vref/ T 20 mVTotal Output Variation Includes Line and Load Regulation over Temperature Circuit Current (Vref = 0 V, TJ = +25 C)ISC 80100mAOutput Noise Voltage (10 Hz f 10 kHz, TJ = +25 C)Vn 40200 VrmsLong Term Stability (TJ = +125 C) (Note 4)S 2050mV/khrOSCILLATOR SECTION (Note 5, unless otherwise noted.)Initial Accuracy (TJ = +25 C) Stability with Voltage(+ V VCC +35 V) foscDVCC Stability with Temperature foscDT %Minimum Frequency (RT = 150 k , CT = F)fmin 50 HzMaximum Frequency (RT = k , CT = nF)fmax400 kHzCurrent Mirror (IRT = mA) VClock Width (TJ = +25 C) sSync Input Current (Sync Voltage = + V) AMPLIFIER SECTION (VCM = + V)Input Offset VoltageVIO Bias CurrentIIB AInput Offset CurrentIIO ADC Open Loop Gain (RL 10 M )

10 AVOL6075 dBLow Level Output VoltageVOL Level Output VCommon Mode Rejection Ratio (+ V VCM + V)CMRR6075 dBPower Supply Rejection Ratio (+ V VCC +35 V)PSRR5060 dBPWM COMPARATOR SECTIONM inimum Duty CycleDCmin 0%Maximum Duty CycleDCmax4549 %Input Threshold, Zero Duty Cycle (Note 5) VInput Threshold, Maximum Duty Cycle (Note 5)Vth Bias CurrentIIB A3. Tlow = 0 Thigh = +70 C4. Since long term stability cannot be measured on each device before shipment, this specification is an engineering estimate of averagestability from lot to Tested at fosc = 40 kHz (RT = k , CT = F, RD = 0 ).