SG3525A - Pulse Width Modulator Control Circuit

1 SG3525A . Pulse Width Modulator Control Circuit The SG3525A Pulse Width Modulator Control Circuit offers improved performance and lower external parts count when implemented for controlling all types of switching power supplies. The on chip + V reference is trimmed to 1% and the error amplifier has an input common mode voltage range that includes the reference voltage, thus eliminating the need for external divider MARKING. DIAGRAMS. resistors. A sync input to the oscillator enables multiple units to be slaved or a single unit to be synchronized to an external system clock. 16. A wide range of deadtime can be programmed by a single resistor PDIP 16 SG3525AN. connected between the CT and Discharge pins. This device also N SUFFIX AWLYYWW. features built in soft start circuitry, requiring only an external timing CASE 648. capacitor. A shutdown pin controls both the soft start circuitry and the 16 1. 1. output stages, providing instantaneous turn off through the PWM latch with pulsed shutdown, as well as soft start recycle with longer 16.

2 Shutdown commands. The under voltage lockout inhibits the outputs and the changing of the soft start capacitor when VCC is below 16 SOIC 16L. SG3525A . nominal. The output stages are totem pole design capable of sinking DW SUFFIX. AWLYYWW. and sourcing in excess of 200 mA. The output stage of the SG3525A CASE 751G. features NOR logic resulting in a low output for an off state. 1. 1. Features V to 35 V Operation A. WL. = Assembly Location = Wafer Lot V Trimmed Reference YY = Year 100 Hz to 400 kHz Oscillator Range WW = Work Week Separate Oscillator Sync Pin Adjustable Deadtime Control input Undervoltage Lockout PIN CONNECTIONS. Latching PWM to Prevent Multiple Pulses Inv. input 1 16 Vref Pulse by Pulse Shutdown Dual Source/Sink Outputs: 400 mA Peak Noninv. input 2 15 VCC. Pb Free Packages are Available* Sync 3 14 Output B. OSC. Output 4 13 VC. CT 5 12 Ground RT 6 11 Output A. Discharge 7 10 Shutdown Soft Start 8 9 Compensation (Top View).

3 ORDERING INFORMATION. See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2005 1 Publication Order Number: January, 2005 Rev. 5 SG3525A /D. SG3525A . 16 VC. Vref To Internal 13. 15 Circuitry Reference Under . VCC Output A. Regulator Voltage 12 Lockout Ground 11. NOR. 4. OSC Output 3 Q. Sync 6 Oscillator F/F. RT Q NOR 14. 5 Output B. CT. 7. Discharge R. 9 + S. Compensation PWM Latch SG3525A Output Stage 1 . INV. input . Error 50 A S. 2 Amp Noninv. input + VREF. 8. CSoft Start 10 Shutdown Figure 1. Representative Block Diagram ORDERING INFORMATION. Device Package Shipping . SG3525AN PDIP 16 25 Units / rail SG3525 ANG PDIP 16 25 Units / rail (Pb Free).

4 SG3525 ADW SOIC 16L 47 Units / rail SG3525 ADWG SOIC 16L 47 Units / rail (Pb Free). SG3525 ADWR2 SOIC 16L 1000 Tape & Reel SG3525 ADWR2G SOIC 16L 1000 Tape & Reel (Pb Free). For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. 2. SG3525A . MAXIMUM RATINGS. Rating Symbol Value Unit Supply Voltage VCC +40 Vdc Collector Supply Voltage VC +40 Vdc Logic Inputs to + V. Analog Inputs to VCC V. Output Current, Source or Sink IO 500 mA. Reference Output Current Iref 50 mA. Oscillator Charging Current mA. Power Dissipation PD mW. TA = +25 C (Note 1) 1000. TC = +25 C (Note 2) 2000. Thermal Resistance, Junction to Air R JA 100 C/W. Thermal Resistance, Junction to Case R JC 60 C/W. Operating Junction Temperature TJ +150 C. Storage Temperature Range Tstg 55 to +125 C. Lead Temperature (Soldering, 10 seconds) TSolder +300 C.

5 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. 1. Derate at 10 mW/ C for ambient temperatures above +50 C. 2. Derate at 16 mW/ C for case temperatures above +25 C. RECOMMENDED OPERATING CONDITIONS. Characteristics Symbol Min Max Unit Supply Voltage VCC 35 Vdc Collector Supply Voltage VC 35 Vdc Output Sink/Source Current IO mA. (Steady State) 0 100. (Peak) 0 400. Reference Load Current Iref 0 20 mA. Oscillator Frequency Range fosc 400 kHz Oscillator Timing Resistor RT 150 k . Oscillator Timing Capacitor CT F. Deadtime Resistor Range RD 0 500 . Operating Ambient Temperature Range TA 0 +70 C. APPLICATION INFORMATION. Shutdown Options (See Block Diagram, page 2) latch is immediately set providing the fastest turn off signal Since both the compensation and soft start terminals to the outputs; and a 150 A current sink begins to discharge (Pins 9 and 8) have current source pull ups, either can the external soft start capacitor.

6 If the shutdown command readily accept a pull down signal which only has to sink a is short, the PWM signal is terminated without significant maximum of 100 A to turn off the outputs. This is subject discharge of the soft start capacitor, thus, allowing, for to the added requirement of discharging whatever external example, a convenient implementation of Pulse by Pulse capacitance may be attached to these pins. current limiting. Holding Pin 10 high for a longer duration, An alternate approach is the use of the shutdown circuitry however, will ultimately discharge this external capacitor, of Pin 10 which has been improved to enhance the available recycling slow turn on upon release. shutdown options. Activating this Circuit by applying a Pin 10 should not be left floating as noise pickup could positive signal on Pin 10 performs two functions: the PWM conceivably interrupt normal operation. 3. SG3525A . ELECTRICAL CHARACTERISTICS (VCC = +20 Vdc, TA = Tlow to Thigh [Note 3], unless otherwise noted.)

7 Characteristics Symbol Min Typ Max Unit REFERENCE SECTION. Reference Output Voltage (TJ = +25 C) Vref Vdc Line Regulation (+ V VCC +35 V) Regline 10 20 mV. Load Regulation (0 mA IL 20 mA) Regload 20 50 mV. Temperature Stability Vref/ T 20 mV. Total Output Variation Includes Line and Load Regulation over Temperature Vref Vdc Short Circuit Current (Vref = 0 V, TJ = +25 C) ISC 80 100 mA. Output Noise Voltage (10 Hz f 10 kHz, TJ = +25 C) Vn 40 200 Vrms Long Term Stability (TJ = +125 C) (Note 4) S 20 50 mV/khr OSCILLATOR SECTION (Note 5, unless otherwise noted.). Initial Accuracy (TJ = +25 C) %. Frequency Stability with Voltage fosc %. (+ V VCC +35 V) DVCC. Frequency Stability with Temperature fosc %. DT. Minimum Frequency (RT = 150 k , CT = F) fmin 50 Hz Maximum Frequency (RT = k , CT = nF) fmax 400 kHz Current Mirror (IRT = mA) mA. Clock Amplitude V. Clock Width (TJ = +25 C) s Sync Threshold V. Sync input Current (Sync Voltage = + V) mA.

8 ERROR AMPLIFIER SECTION (VCM = + V). input Offset Voltage VIO 10 mV. input Bias Current IIB 10 A. input Offset Current IIO A. DC Open Loop Gain (RL 10 M ) AVOL 60 75 dB. Low Level Output Voltage VOL V. High Level Output Voltage VOH V. Common Mode Rejection Ratio (+ V VCM + V) CMRR 60 75 dB. Power Supply Rejection Ratio (+ V VCC +35 V) PSRR 50 60 dB. PWM COMPARATOR SECTION. Minimum Duty Cycle DCmin 0 %. Maximum Duty Cycle DCmax 45 49 %. input Threshold, Zero Duty Cycle (Note 5) Vth V. input Threshold, Maximum Duty Cycle (Note 5) Vth V. input Bias Current IIB A. 3. Tlow = 0 Thigh = +70 C. 4. Since long term stability cannot be measured on each device before shipment, this specification is an engineering estimate of average stability from lot to lot. 5. Tested at fosc = 40 kHz (RT = k , CT = F, RD = 0 ). 4. SG3525A . ELECTRICAL CHARACTERISTICS (continued). Characteristics Symbol Min Typ Max Unit SOFT START SECTION. Soft Start Current (Vshutdown = 0 V) 25 50 80 A.

9 Soft Start Voltage (Vshutdown = V) V. Shutdown input Current (Vshutdown = V) mA. OUTPUT DRIVERS (Each Output, VCC = +20 V). Output Low Level VOL V. (Isink = 20 mA) (Isink = 100 mA) Output High Level VOH V. (Isource = 20 mA) 18 19 . (Isource = 100 mA) 17 18 . Under Voltage Lockout (V8 and V9 = High) VUL V. Collector Leakage, VC = +35 V (Note 6) IC(leak) 200 A. Rise Time (CL = nF, TJ = 25 C) tr 100 600 ns Fall Time (CL = nF, TJ = 25 C) tf 50 300 ns Shutdown Delay (VDS = + V, CS = 0, TJ = +25 C) tds s Supply Current (VCC = +35 V) ICC 14 20 mA. 6. Applies to SG3525A only, due to polarity of output pulses. Vref 16 15 VCC. Reference Regulator Clock 4 Flip/ 13 VC. Flop Sync 3 O Out A. PWM. ADJ. s 11. RT c A. 6 i l Deadtime l , a Ramp 7 (2). t 100 5 o r 14. B. Out B. Comp 10k 9 12. PWM GND. 1 = VIO. 2 = 1(+) 3 = 1( ) 50 A 8 Softstart 1 1. +. 2 2 1 F.. 3 3 E/A 10. 2 Vref V/I Meter +. 1 1 + 2 2. 3 3 DUT. Shutdown Figure 2. Lab Test Fixture 5.

10 SG3525A . 200 500. R D , DEAD TIME RESISTOR ( ).. 100 400. RT, TIMING RESISTOR (k ). 50. 300. * RD = 0 . 20. 200. 10. 6 5 7. RD * 100. RT CT. 0. 10 20 50 100 200 500 1000 2000 5000 10,000 10 20 50 100 200. CHARGE TIME ( s) DISCHARGE TIME ( s). Figure 3. Oscillator Charge Time versus RT Figure 4. Oscillator Discharge Time versus RD. 1 9. V sat , SATURATION VOLTAGE (V). 2 + VCC = +20 V. CP TJ = +25 C. A VOL, VOLTAGE GAIN (dB). 100 RZ 80 60 RZ = 20 k 40. Source Sat, (VC VOH). 20. 0 Sink Sat, (VOL). 20 0. 10 100 k 10 k 100 k M 10 M f, FREQUENCY (Hz) IO, OUTPUT SOURCE OR SINK CURRENT (A). Figure 5. Error Amplifier Open Loop Figure 6. Output Saturation Frequency Response Characteristics Vref 15. 16 VCC. Q1 Q5 Q8. Q3. RT Q3. 6. CT Q6 Q9. 5 Ramp Q4. Inverting 14k To PWM Q1 Q2. input 3 Q10 Q11 25k 1. Sync Blanking To PWM. Noninverting 7 Q14 To Output input Comparator Discharge 400 A 2. Q4 30. Q2 23k 200 A 100 A. Q7 Q12 Q13 250.