Si570/Si571 Data Sheet - Silicon Labs

1 Si 570/ Si 571. 1 0 MH Z TO 1. 4 G H Z I 2C P R O G R A M M A B L E XO/ VC XO. Features Any programmable output Internal fixed crystal frequency frequencies from 10 to 945 MHz and ensures high reliability and low Si5602. select frequencies to GHz aging I2C serial interface Available LVPECL, cmos , LVDS, and CML outputs 3rd generation DSPLL with superior Industry-standard 5x7 mm jitter performance package 3x better frequency stability than Pb-free/RoHS-compliant SAW-based oscillators , , or V supply Applications Ordering Information: SONET/SDH High performance See page 31. xDSL instrumentation 10 GbE LAN/WAN Low-jitter clock generation ATE Optical modules Pin Assignments: Clock and data recovery See page 30.

2 Description (Top View). The Si570 XO/Si571 VCXO utilizes Skyworks Solutions' advanced DSPLL . SDA. circuitry to provide a low-jitter clock at any frequency. The Si570/Si571 are user- programmable to any output frequency from 10 to 945 MHz and select frequencies 7. to 1400 MHz with <1 ppb resolution. The device is programmed via an I2C serial NC 1 6 VDD. interface. Unlike traditional XO/VCXOs where a different crystal is required for each output frequency, the Si57x uses one fixed-frequency crystal and a DSPLL. OE 2 5 CLK . clock synthesis IC to provide any-frequency operation. This IC-based approach allows the crystal resonator to provide exceptional frequency stability and reliability. In addition, DSPLL clock synthesis provides superior supply noise GND 3 4 CLK+.

3 Rejection, simplifying the task of generating low-jitter clocks in noisy environments 8. typically found in communication systems. SCL. Functional Block Diagram Si570. VDD CLK- CLK+. SDA. 7. OE VC 1 6 VDD. Fixed 10-1400 MHz . Frequency DSPLL Clock SDA XO Synthesis SCL OE 2 5 CLK . Si571 only GND 3 4 CLK+. ADC 8. SCL. VC. GND. Si571. Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 Rev. Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice November 15, 2021. Si 570/S i57 1. TABLE OF C ONTENTS. Section Page 1. Detailed Block Diagrams .. 3. 2. Electrical Specifications .. 4. 3. Functional Description .. 14. Programming a New Output Frequency.

4 14. Si570 Programming Procedure .. 18. Si570 Troubleshooting FAQ .. 20. I2C Interface .. 21. 4. Serial Port Registers .. 22. 5. Si570 (XO) Pin Descriptions .. 29. 6. Si571 (VCXO) Pin Descriptions .. 30. 7. Ordering Information .. 31. 8. Si57x Mark Specification .. 32. 9. Outline Diagram and Suggested Pad Layout ..33. 10. 8-Pin PCB Land Pattern .. 34. Revision History .. 35. 2 Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 Rev. Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice November 15, 2021. Si570/Si571 . 1. Detailed Block Diagrams VDD GND. fXTAL. +. M CLKOUT+. DCO HS_DIV N1. fosc CLKOUT . RFREQ. Frequency Control OE. Control SDA.

5 SCL. Interface NVM RAM. Figure 1. Si570 Detailed Block Diagram VDD GND. fXTAL. +. M CLKOUT+. VC ADC DCO HS_DIV N1. VCADC fosc CLKOUT . RFREQ. Frequency Control OE. Control SDA. SCL. Interface NVM RAM. Figure 2. Si571 Detailed Block Diagram Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 3. Rev. Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice November 15, 2021. Si 570/S i57 1. 2. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Test Condition Min Typ Max Unit V option Supply Voltage1 VDD V option V. V option Output enabled LVPECL 120 130. CML 108 117. Supply Current IDD LVDS 99 108 mA. cmos 90 98.

6 TriState mode 60 75. 2, Output Enable (OE) VIH x VDD . Serial Data (SDA), V. VIL Serial Clock (SCL). Operating Temperature Range TA 40 85 C. Notes: 1. Selectable parameter specified by part number. See Section "7. Ordering Information" on page 31 for further details. 2. OE pin includes a 17 k pullup resistor to VDD. See Information . Table 2. VC Control Voltage Input (Si571). Parameter Symbol Test Condition Min Typ Max Unit 33. 45. 90. Control Voltage Tuning Slope1,2,3 KV VC 10 to 90% of VDD ppm/V. 135. 180. 356. BSL 5 1 +5. Control Voltage Linearity4 LVC %. Incremental 10 5 +10. Modulation Bandwidth BW kHz VC Input Impedance ZVC 500 k . 5. Nominal Control Voltage VCNOM @ fO VDD/2 V. Control Voltage Tuning Range VC 0 VDD V.

7 Notes: 1. Positive slope; selectable option by part number. See "7. Ordering Information" on page 31. 2. For best jitter and phase noise performance, always choose the smallest KV that meets the application's minimum APR. requirements. See AN266: VCXO Tuning Slope (KV), Stability, and Absolute Pull Range (APR) for more information. 3. KV variation is 10% of typical values. 4. BSL determined from deviation from best straight line fit with VC ranging from 10 to 90% of VDD. Incremental slope is determined with VC ranging from 10 to 90% of VDD. 5. Nominal output frequency set by VCNOM = 1/2 x VDD. 4 Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 Rev. Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice November 15, 2021.

8 Si570/Si571 . Table 3. CLK Output Frequency Characteristics Parameter Symbol Test Condition Min Typ Max Unit Programmable Frequency LVPECL/LVDS/CML 10 fO MHz Range1,2 cmos 10 160. 7 7. 20 +20. Temperature Stability1,3 TA = 40 to +85 C ppm 50 +50. 100 +100. Initial Accuracy ppm Frequency drift over first year 3 ppm Aging fa Frequency drift over 20-year life 10 ppm Temp stability = 7 ppm 20 ppm Total Stability Temp stability = 20 ppm ppm Temp stability = 50 ppm ppm Absolute Pull Range1,3 APR 12 375 ppm Power up Time4 tOSC 10 ms Notes: 1. See Section "7. Ordering Information" on page 31 for further details. 2. Specified at time of order by part number. Three speed grades available: Grade A covers 10 to 945 MHz, 970 to 1134 MHz, and 1213 to MHz.

9 Grade B covers 10 to 810 MHz. Grade C covers 10 to 280 MHz. 3. Selectable parameter specified by part number. 4. Time from power up or tristate mode to fO. Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 5. Rev. Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice November 15, 2021. Si 570/S i57 1. Table 4. CLK Output Levels and Symmetry Parameter Symbol Test Condition Min Typ Max Unit VO mid-level VDD VDD V. 1. LVPECL Output Option VOD swing (diff) VPP. VSE swing (single-ended) VPP. VO mid-level V. LVDS Output Option2. VOD swing (diff) VPP. V option mid-level VDD V. VO. V option mid-level VDD V. CML Output Option2. V option swing (diff) VPP.

10 VOD. V option swing (diff) VPP. VOH IOH = 32 mA x VDD VDD V. cmos Output Option3. VOL IOL = 32 mA V. LVPECL/LVDS/CML 350 ps Rise/Fall time (20/80%) tR, tF. cmos with CL = 15 pF 1 ns LVPECL: VDD V (diff). Symmetry (duty cycle) SYM LVDS: V (diff) 45 55 %. cmos : VDD/2. Notes: 1. Rterm = 50 to VDD V. 2. Rterm = 100 (differential). 3. CL = 15 pF. 6 Skyworks Solutions, Inc. Phone [781] 376-3000 Fax [781] 376-3100 Rev. Skyworks Proprietary Information Products and Product Information are Subject to Change Without Notice November 15, 2021. Si570/Si571 . Table 5. CLK Output Phase Jitter (Si570). Parameter Symbol Test Condition Min Typ Max Unit Phase Jitter (RMS)1 J 12 kHz to 20 MHz (OC-48) ps for FOUT > 500 MHz 50 kHz to 80 MHz (OC-192) Phase Jitter (RMS)1 J 12 kHz to 20 MHz (OC-48) ps for FOUT of 125 to 500 MHz 50 kHz to 80 MHz (OC-192)2 Phase Jitter (RMS) J 12 kHz to 20 MHz (OC-48)2 ps for FOUT of 10 to 160 MHz 2.