TFA9879 Mono BTL class-D audio amplifier for portable ...

1 1. IntroductionThe TFA9879 is a high -efficiency filter-free mono class-D audio amplifier with two separate digital inputs for mobile General descriptionThe TFA9879 contains a processor that supports a range of sound processing features including a 5-band parametric equalizer, separate bass and treble control, a dynamic range compressor, soft clip control and volume control. Excellent audio performance combined with high power supply rejection Ratio (PSRR) is achieved through the use of a closed loop independent digital audio inputs (I2S-bus / PCM / IOM2) are available for connecting both a baseband and a multimedia processor. The TFA9879 is available in a HVQFN24 Features and General features Closed loop amplifier for: high power supply rejection ratio Excellent audio performance Digital input for high RF immunity high efficiency for maximizing battery life Wide supply voltage range (fully operational from V to V) Delivers high output power into 4 and 8 load impedances Phase-Locked Loop (PLL).

2 No system clock required Protection including diagnostics via I2C-bus: OverCurrent Protection (OCP) to protect against short circuits across the speaker, to the supply line or to ground OverTemperature Protection (OTP) Digital inputs protected with UnderFrequency Protection (UFP), OverFrequency Protection (OFP) and Invalid Bit-clock Protection (IBP) Pop noise free at power -up/ power down, during sample rate switching and when switching between digital inputs Four separate I2C-bus addresses for multi-channel applicationsTFA9879 Mono BTL class-D audio amplifier for portable applications with digital inputRev. 02 15 October 2010 Product data sheetTFA9879 All information provided in this document is subject to legal disclaimers. NXP 2010. All rights data sheetRev. 02 15 October 2010 2 of 60 NXP SemiconductorsTFA9879 Mono BTL class-D audio amplifier with digital input V / V tolerant digital inputs Only three external components Programmable Digital Sound Processor (DSP) Digital volume control ( 70 dB to +24 dB) Digital parametric 5-band equalizer Bass and treble control ( 18 dB to +18 dB) Dynamic range compressor: Programmable attack and release levels Programmable attack and release rates Soft and hard mute control Programmable DC blocking via high -pass filter power limiter (0 dB to 124 dB in dB steps) Zero crossing volume control Stereo-to-mono down-mix Interface format support for digital audio inputs I2S formats (fs = 8 kHz to 96 kHz): Philips standard I2S-bus Japanese I2S-bus MSB-justified Sony I2S-bus LSB-justified PCM / IOM2 formats (fs = 8 kHz or fs = 16 kHz): Long frame sync Short frame sync4.

3 Applications Mobile phones portable Navigation Devices (PND) PDAs Notebooks portable gaming devices MP3 and MP4 playersTFA9879 All information provided in this document is subject to legal disclaimers. NXP 2010. All rights data sheetRev. 02 15 October 2010 3 of 60 NXP SemiconductorsTFA9879 Mono BTL class-D audio amplifier with digital input5. Quick reference data [1]After switching from Off/ amplifier mode to power -down Ordering information Table reference dataAll parameters are guaranteed for VDDD = V; VDDP = V; RL = 8 ; LL = 44 H; fi = 1 kHz; fs = 48 kHz; clip control off; Tamb = 25 C unless otherwise supply voltageon pin supply voltageon pin currenton pin VDDP; amplifier mode with load; soft mute mAon pin VDDP; power -down mode--20 AIDDD digital supply currenton pin VDDD; amplifier pin VDDD; power -down mode[1]-515 APo(RMS)RMS output powerRL=8 THD + N = 1 % + N = 10 % THD+N=1% +N=10% ; VDDP = VTHD+N=1% +N=10% ; VDDP = VTHD+N=1% + N = 10 % ; VDDP = VTHD+N=1% +N=10% ; VDDP = VTHD+N=1% + N = 10 % pooutput power efficiencyPo(RMS) = 850 mW-92-%Table informationType numberPackageNameDescriptionVersionTFA98 79 HNHVQFN24plastic thermal enhanced very thin quad flat package; no leads; 24 terminals.

4 Body 4 x 4 x mmSOT616_3 TFA9879 All information provided in this document is subject to legal disclaimers. NXP 2010. All rights data sheetRev. 02 15 October 2010 4 of 60 NXP SemiconductorsTFA9879 Mono BTL class-D audio amplifier with digital input7. Block diagram Fig diagramI2 CCONTROLDIGITALAUDIORECEIVERHIGHPASSFILT ER5 BANDEQUALIZERBASSTREBLEBOOSTPOWERLIMITER MUXPWMVDDPOUTAOUTB7, 8109 PLL2ndORDERLOOPVOLUMECONTROLDRCDSP123 VDDDTFA98792202122171819 SCLSDI1 SCK1 LRCK1 SDI2 SCK2 LRCK21624 ADSEL1 SDAPROTECTIONCIRCUITS:OCPOTPOFPUFPIBP6, , 122ndORDERLOOP010aaa542 TEST13 TEST215 TEST354 ADSEL2 DAPTFA9879 All information provided in this document is subject to legal disclaimers. NXP 2010. All rights data sheetRev. 02 15 October 2010 5 of 60 NXP SemiconductorsTFA9879 Mono BTL class-D audio amplifier with digital input8. Pinning Pinning Pin description (1) Exposed Die Attach Paddle (DAP)Fig configuration010aaa582 TFA9879 Transparent top 1index area613514415316217118789101112242322212 019 DAP(1)Table descriptionSymbolPin Pin TypeDescriptionSDA1 IOI2C-bus data input/outputSCL2II2C-bus bit clock inputTEST13 Itest signal input 1; for test purposes only; connect to PCB groundADSEL24 Iaddress selection input 2 TEST35 Itest signal input 3; for test purposes only; connect to PCB connected; connect to PCB groundVDDP7, 8 Panalog supply voltage ( V to V)OUTB9 Ooutput B (negative)OUTA10 Ooutput A (positive)GNDP11, 12 Panalog ground, PCB ground V analog stabilizer connected; connect to PCB groundTEST215 Itest signal input 2; for test purposes only.

5 Connect to PCB groundADSEL116 Iaddress selection input 1 SDI217 Idigital audio data input 2 SCK218 Idigital audio bit clock input 2 LRCK219 Idigital audio word select input 2 SDI120 Idigital audio data input 1 SCK121 Idigital audio bit clock input 1 LRCK122 Idigital audio word select input 1 TFA9879 All information provided in this document is subject to legal disclaimers. NXP 2010. All rights data sheetRev. 02 15 October 2010 6 of 60 NXP SemiconductorsTFA9879 Mono BTL class-D audio amplifier with digital input9. Functional descriptionThe TFA9879 is a high -efficiency mono Bridge Tied Load (BTL) class-D amplifier with digital audio inputs. It supports all commonly used key functional blocks of the TFA9879 are shown in Figure 1. In the digital domain, the audio signal is processed and converted into a Pulse Width Modulated (PWM) signal using a 3-level modulation. In the analog domain, the PWM signal is amplified using a second order feedback audio signal-processing path is described below: 1.

6 The MUX selects the serial interface input to be used. 2. The digital audio receiver translates the serial input signal into a standard internal mono audio The programmable high -pass filter blocks DC signals and low frequency The volume control provides both gain and attenuation functionality and can be adjusted by the user or dynamically via the Dynamic Range Compressor (DRC). The volume control can be used to adjust the signal level between 70 dB and +24 The 5-band parametric equalizer can be used to equalize the mono audio stream. It can be used for speaker transfer curve compensation to optimize the audio performance of the The bass and treble boost function provides another way to adjust the The power limiter limits the maximum output signal of the TFA9879 . The power limiter settings are 0 dB to 124 dB in steps of dB. This function can be used to limit the maximum output power delivered to the speakers at a fixed supply voltage and speaker The PWM controller block converts the audio signal into a 3-level modulated PWM signal.

7 The 3-level modulation provides a high signal-to-noise performance and eliminates clock jitter The second order feedback loop ensures excellent audio performance and high power supply rejection The H-BRIDGE allows the TFA9879 to deliver the required output power between terminals OUTA and internal clocks of the TFA9879 are derived from the digital audio interface (SCK1 and SCK2) using a PLL. The reference input for the PLL is selected via the digital input audio signal path can be selected via the I2C-bus PLL block generates the system supply voltage ( V)GNDD24 Pdigital ground, PCB ground referenceDAP-Pexposed Die Attached Paddle (DAP); connect to PCB groundTable description ..continuedSymbolPin Pin TypeDescriptionTFA9879 All information provided in this document is subject to legal disclaimers. NXP 2010. All rights data sheetRev. 02 15 October 2010 7 of 60 NXP SemiconductorsTFA9879 Mono BTL class-D audio amplifier with digital inputThe following protection circuits are built into the TFA9879 : OverTemperature Protection (OTP) OverCurrent Protection (OCP) UnderFrequency Protection (UFP) OverFrequency Protection (OFP) Invalid Bit-clock Protection (IBP) Operating modesThe TFA9879 supports the following operating modes, which are controlled via the I2C-bus interface: power -down mode, used to switch off the device; current consumption is reduced to a minimum; the I2C-bus remains operational; the PWM outputs are disabled.

8 Off mode, in which the class-D amplifier is switched off; the TFA9879 is completely biased and the PWM outputs are disabled. amplifier mode, in which the digital inputs are used to generate a signal between OUTA and TFA9879 device control settings are detailed in Table power -up/ power -downThe power -up and power -down timing of the TFA9879 is illustrated in Figure 3. The external power supply levels, VDDP and VDDD, should be within the specified operating ranges before the operating mode is selected. Bit POWERUP in the Device control register (Table 21) must be set to 1 before the operating mode can be selected via bits OPMODE. After the turn-on delay (td(on)), the device automatically generates a soft un-mute function. A soft mute function is generated when OPMODE is set to 0. The TFA9879 should be set to power -down mode before the power supplies are disconnected or turned off. TFA9879 All information provided in this document is subject to legal disclaimers. NXP 2010. All rights data sheetRev.

9 02 15 October 2010 8 of 60 NXP SemiconductorsTFA9879 Mono BTL class-D audio amplifier with digital input Supported Digital audio data formatsThe TFA9879 supports a commonly used range of I2S, PCM and IOM2 digital audio data formats. The I2S formats, selected via bits I2S_SET in the Serial interface control register (Ta b l e 2 2), are listed in Table 4. The PCM/IOM2 formats are listed in Ta b l e 5. The TFA9879 automatically detects the number of slots by measuring the ratio between the sync frequency (8 kHz) and the data clock. Ta b l e 2 4 details the I2C settings for the PCM/IOM2 timingfiltered BTLoutput signalOUTA, OUTB serial interfaceinput signalsI2C POWERUP(00h, bit 0)VDDP, VDDDI2C OPMODE(00h, bit 3)operatingtd(soft_mute)010aaa653td(on)t d(mute_off) TFA9879 All information provided in this document is subject to legal disclaimers. NXP 2010. All rights data sheetRev. 02 15 October 2010 9 of 60 NXP SemiconductorsTFA9879 Mono BTL class-D audio amplifier with digital input Table digital audio data formatsSCK frequencyInterface format (MSB first)Supported data format32 fsI2S (Philips) standardup to 16-bit data32 fsMSB-justified up to 16-bit data32 fsLSB-justified - 16 bits16-bit data64 fsI2S (Philips)

10 Standardup to 24-bit data64 fsMSB-justified up to 24-bit data64 fsLSB-justified - 16 bits16-bit data64 fsLSB-justified - 18 bits18-bit data64 fsLSB-justified - 20 bits20-bit data64 fsLSB-justified - 24 bits24-bit dataFig digital audio data formats16 MSB B2B3B4B5B6 LEFTLSB-JUSTIFIED FORMAT 20 BITSWSBCKDATARIGHT151817201921B19 LSB16 MSB B2B3B4B5B6151817201921B19 LSBMSBMSBB22112 3 LEFTI2S-BUS FORMATWSBCKDATARIGHT3 MSB B2010aaa45816B5B6B7B8B9B10 LEFTLSB-JUSTIFIED FORMAT 24 BITSWSBCKDATARIGHT15181720192221232421B3 B4 MSBB2B23 LSB16B5B6B7B8B9B1015181720192221232421B3 B4 MSBB2B23 LSB16 MSBB2 LEFTLSB-JUSTIFIED FORMAT 16 BITSWSBCKDATARIGHT1521B15 LSB16 MSB B21521B15 LSB16 MSB B2B3B4 LEFTLSB-JUSTIFIED FORMAT 18 BITSWSBCKDATARIGHT15181721 MSB B2B3B4B17 LSB1615181721B17 LSBMSB-JUSTIFIED FORMATWSLEFTRIGHT321321 MSBB2 MSBLSBLSBMSBB2B2 BCKDATATFA9879 All information provided in this document is subject to legal disclaimers. NXP 2010. All rights data sheetRev. 02 15 October 2010 10 of 60 NXP SemiconductorsTFA9879 Mono BTL class-D audio amplifier with digital input Table audio data formatsNumber of slotsfs (kHz)Sync frequency (kHz) on LRCK pinSupported data formatsData clock (kHz) on SCK pin28 or 1688-bit data12828 or 1688-bit data12848 or 1688-bit data25648 or 1688-bit data25668 or 1688-bit data38488 or 1688-bit data512128 or 1688-bit data768168 or 1688-bit data1024reserved28 or 16816-bit data25638 or 16816-bit data38448 or 16816-bit data51268 or 16816-bit data76888 or 16816-bit data1024128 or 16816-bit data1536128 or 16816-bit data1536 Fig digital audio data formatsMSBLRCKSCKSDILSB MSBB2B2 LSB MSBSHORT SYNC PCM/IOM2 FORMATSlot 0 Slot 1 Slot 2 Slot N 1 Slot NB2 LSB MSBB2 LSBMSBLRCKSCKSDILSB MSBB2B2 LSB MSBLONG SYNC PCM/IOM2 FORMATSlot 0 Slot 1 Slot 2 Slot N 1 Slot N010aaa652B2 LSB MSBB2 LSBTFA9879 All information provided in this document is subject to legal disclaimers.