The Delay-Locked Loop

1 A C ircu it for All Seasons Behzad Razavi The Delay-Locked Loop D. Delay-Locked loops (DLLs) can be considered as feedback circuits that phase lock an output to an input without the use of an oscillator. In some applications, DLLs are neces- to adjust the delay and force DT. toward zero. This conjecture leads us to the arrangement depicted in Fig u r e 2(c). He r e , a phase detector mea- of the phase/frequency detector (PFD), charge pump (CP), and capacitor pro- vides an infinite gain, thus driving the skew toward zero. The variable- delay stage is sary or preferable over phase- locked sures the skew and The origins of realized as a voltage- loops (PLLs), with their advantages adjusts t he delay of DLLs can be controlled delay line including lower sensitivity to supply B 2 t o r e d u c e DT. A s traced to a paper (VCDL). Figure 2(e). noise and lower phase noise. This with PLLs, the low-pass published shows an example of article deals with fundamental DLL filter attenuates the in 1961.

2 VCDL design emp . design concepts. high-frequency compo- loying varactors for de- The origins of DLLs can be traced nents generated by the lay control. While the to a paper published in 1961 [1]. The PD. This circuit exemplifies a simple DLL does not require frequency authors present the topology shown Delay-Locked loop. detection, the PFD provides a con- in Figure 1 as a delay -lock discrimi- The residual phase error in Fig- venient interface with the CP. As ex- nator operating on random signals. ure 2(c) depends on the loop gain, , the plained next, no resistor is necessary The feedback loop consists of a con- gain of the PD, K PD, and the gain of the in series with C 1 . This DLL archi- trolled delay line, a multiplier acting variable- delay stage. The latter is de- tecture is commonly used in high- as a phase detector (PD), and a low- fined as K DL = 2z/2 Vcont, where z is speed systems. pass filter. The use of DLLs in mod- the stage's delay in ra d i a ns. Rath- The DLL of Figure 2(d) is of first ern CMOS design evidently began er than attempt to maximize order, facing no stability issues.

3 More- with the work by Bazes in 1985 [2] K PD K DL, we can add an integrator to over, it benefits from the lower phase and Johnson and Hudson in 1988 [3]. the loop. Drawing upon our knowl- noise and supply sensitivity of delay e d g e o f PLLs, we thus construct lines compared to oscillators. Basic Idea the architecture shown in Figure 2(d), In contrast to PLLs, Delay-Locked Suppose, as shown in Figure 2(a), an where the cascade consisting loops do not generate a frequency;. input clock travels on a long inter- connect, experiencing a significant skew, DT. How do we align CK out with Received Waveform Multiplier CK in ? Since the clock is periodic, As [t + T (t )] + n (t ). we surmise that an additional delay x (t ) Low-Pass delay Estimate can be introduced to make the total Filter F (p ). ". aT (t ). delay equal to one clock cycle [Fig- ure 2(b)]. To set the delay properly, ks [t + T (t )]. we can view DT as an error that must be suppressed by means of negative delay Control feedback.

4 That is, if the phase of CK out is compared to that of CK in, Reference Controlled delay Line the resulting er ror ca n be used Differentiate Gain gd = 1/ sec/Volt ks (t ). ks (t ). Digital Object Identifier Date of publication: 13 August 2018 Figure 1: An early DLL reported in [1]. IEEE SOLID-STATE CIRCUITS MAGAZINE su m m e r 2 0 18 9. TCK. CKin Long Interconnect CKout CKin B1 B2 CKout t T. (a). Variable delay Stage CKin CKin B1 B2 CKout CKout Vcont TCK t (b). VCDL. CKin B1 B2 CKout CKin B1 B2 CKout R1 Vcont Vcont PD PFD CP. C1 C1. (c) (d). CKin CKout Vcont (e). Figure 2: (a) An interconnect with skew, (b) the correction of skew by a delay stage, (c) a simple feedback system for controlling the delay line, (d) a basic DLL, and (e) a VCDL implementation example. rather, they simply delay the input. Loop Dynamics time constant, allowing the approxi- As such, DLLs are less versatile than We wish to analyze the dynamic be mation exp (- TCK s) . 1. PLLs. For example, in practice, a DLL havior of the DLL shown in Figure 3(a).

5 How about the path from Vcont would not be able to generate a 5-GHz In the locked state, the phase differ- to CK out ? If we apply a step at Vcont clock from a 20-MHz reference. ence between CK in and CK out is con- in Figure 2(e), how long does it take Another drawback of DLLs is stant and, in principle, equal to zero. to affect the output phase? From the that they allow the input duty cycle Thus, the VCDL provides a delay of waveforms shown in Figure 3(c), we error to propagate to the output. one clock period, TCK . recognize that this path too has a In fact, the delay line may further Before delving into the overall delay of at most one TCK . Based on increase this error. Thus, the VCDL loop dynamics, let us understand these observations, we can construct is typically preceded or followed those of the VCDL itself. The circuit an approximate, static model for the by a duty cycle correction stage. A has a clock input and a control input. VCDL; as shown in Figure 3(d), it sim- third drawback of DLLs is that they What happens if CK in in Figure 2(e) ply adds a phase equal to K DL Vcont operate the PFD a nd the CP at incurs a phase step?

6 This step propa- to the input phase. (The one-cycle high speeds. gates through the chain and emerges delay is neglected here.). The dynamic behavior of DLLs at the output TCK seconds later [Fig- It is instructive to first examine determines how they respond to such ure 3(b)]. That is, the transfer func- the overall DLL's response qualita- effects as input phase noise, and sup- tion associated with this path can be tively. If the phase of CK in in Fig- ply noise. We therefore study this expressed as exp (-TCK s) . In practice, ure 3(a) fluctuates slowly, the DLL. behavior in the next section. TCK is much less than the overall DLL maintains a high loop gain, keeping 10 su m m e r 2 0 18 IEEE SOLID-STATE CIRCUITS MAGAZINE. TCK. Input Phase CKin VCDL CKout Step out in CKin Vcont PFD CP. CKout C1. t (a) (b). CKin CKout in VCDL out = KDLV cont + in Vcont Vcont t (c) (d). Figure 3: (a) A DLL with a VCDL, (b) the propagation of input phase step to output, (c) the propagation of step on Vcont to output, and (d) a linear model of a VCDL.

7 CK out aligned with CK in . That is, the We should remark that some DLLs Effect of Supply Noise closed-loop transfer function has apply an independent reference The principal effect of supply noise, a unity magnitude for slow phase clock to the PFD and do not follow VDD (t), in DLLs is to modulate the variations. Now suppose CK in expe- these dynamics [4]. delay of the VCDL. How does the DLL. riences very fast phase changes. The aforementioned study reveals of Figure 3(a) respond to VDD (t) ? If Then, the DLL has little loop gain, two points: 1) DLLs do not generally the noise varies slowly, the loop has Vcont d o e s n ot c h a n ge , a n d CK in face stability issues and can oper- enough strength to keep z out close to simply propagates to CK out . In this ate with a wide range of values for z in, , Vcont opposes VDD (t) and z out case, too, the closed-loop response I p and C 1, and 2) the lack of filtering is around unity because the input ability precludes the use of the fore- phase changes appear at the output going DLLs in applications where the VDD.

8 With only a delay of TCK seconds. We input jitter must be removed. The thus conclude that DLLs exhibit an latter issue is resolved by a different KVDD. all-pass response, a point of contrast DLL architecture [4]. to the low-pass behavior of PLLs. out in = 0. The all-pass nature of DLLs can also be confirmed mathematically. For the KDL. DLL of Figure 3(a), we draw the phase +. Ip model as shown in Figure 4(a), noting that in out c1s Vcont Vcont is given by (z in - z out) [I p / (C 1 s)], where I p denotes the charge pump cur- KDL. + (a). rent, and hence Ip out c1s Vcont Ip VDD. z in + (z in - z out) K DL = z out . (1). C1 s (a) KVDD. That is, out in K DL I p . - (z in - z out) = (z in - z out) , (2) IpKDL. C1 s c1. (b) (b). which implies z in = z out . In prac- tice, the response exhibits a small Figure 4: (a) A linear model of DLL and Figure 5: (a) The supply noise in a DLL and amount of peaking [Figure 4(b)] [4]. (b) the DLL phase response. (b) the DLL phase response. IEEE SOLID-STATE CIRCUITS MAGAZINE su m m e r 2 0 18 11.

9 Is not affected. For high-frequency z out K VDD C 1 s where f0 is the oscillation frequency (s) = . (4). noise, on the other hand, the loop gain VDD C 1 s + I p K DL (Figure 6). We conclude that the ring drops, and z out is directly modu- produces much higher phase noise. lated by VDD . Plotted in Figure 5(b), the response One interpretation of this result is Let us define for the VCDL a gain begins to flatten out beyond the pole that, in a ring, an edge continues from VDD to z out as K VDD = 2z out /2 VDD. frequency, ~ p = I p K DL /C 1 . We must to accumulate phase noise as it cir- Shown in Figure 5(a) is the DLL model therefore choose a high value for ~ p culates, whereas, in a delay line, an with supply noise and z in = 0. Be g in so as to maximize the supply rejection. edge experiences the phase noise of ning from the output, we can write the delay stages only once before it Vcont as - z out [I p / (C 1 s)] and hence Effect of Phase Noise reaches the output [6]. DLLs are generally considered to gen- S econd, we model t he VCDL.

10 Ip erate much less phase noise than phase noise as shown in Figure 7(a). - z out K + VDD K VDD = z out . (3). C 1 s DL PLLs, but the comparison must be and write done carefully. We begin with the Ip It follows that input phase noise. As exemplified by - z out K + z n, DL = z out, (6). C 1 s DL. the transfer function plotted in Fig- ure 4(b), this noise experiences no obtaining attenuation and simply propagates to the output. z out C1 s S ,ring (s) = . (7). The case of the VCDL phase noise z n, DL C 1 s + I p K DL. Phase locked is more interesting. We make two ob- Oscillator servations. First, as shown in [5], the Similar to the effect of supply phase noise of a delay line, S z,DL, and noise, this result indicates a first- S ,DL. that of a ring oscillator using such a order high-pass behavior [Figure 7(b)]. line, S z,ring, are related as follows: As expected, the loop rejects slow f0 f0 + f f phase fluctuations caused by the VCDL. In general, the dominant source Figure 6: The comparison of ring oscillator f0 2 of phase noise in VCDLs is the sup p.