Universal Footprint for SO8FL Package - ON …

1 Semiconductor Components Industries, LLC, 2015 February, 2015 Rev. 11 Publication Order Number:AND9137/DAND9137/DUniversal Footprint forSO8FL PackageIntroductionIn the past few years the need to increase power density inconverter designs has made the DFN, QFN, and LFPAK packages very popular among designers of DC DCconverters. That trend was followed by every PowerSemiconductor vendor and has created an interestingproblem. Every vendor has come up with their own versionon the industry standard 5 6 mm Footprint , and althougheach Package design meets the basic pin out requirements,each contains small variations that makes themincompatible and requires the creation for a UniversalFootprint to assist the end users to accommodate more thanone supplier in their OverviewThe ON Semiconductor SO8FL Package is a QFNpackage also known in the industry as the Power-SO8, it wascreated to allow a large die, basically as large as a DPAK, tofit into a standard SO8IC Footprint .

2 This Package uses a leadframe design that allows the leads to stick out beyond themolded body size. This feature allows the customer to seethe solder fillet during visual inspection. See Figure 1 1. The Underside of an SO8FL PackageIn the Package the die is soldered to a large tab forming theelectrical DRAIN connection and a low thermal resistancepath to the PCB. A top-clip is soldered to the top of the dieproviding the SOURCE connection once the clip is attachedto the lead frame to provide a low resistance, low inductanceand also a low thermal resistance path to the PCB. At last theGATE is connected to the lead frame via a vendors have their own realization for this Package ,the common part is the attachment of the silicon die to a tabto create the DRAIN connection, then the SOURCE andGATE connections are made with Aluminum wire-bonding,Copper ribbon bonding, Copper clips and Gold bumping,Copper wire bonding, Copper clip and wire bond.

3 Figure 2has some examples of these interesting variation is the LFPAK, in this Package thesilicon is soldered to the DRAIN tab forming the electricalDRAIN connection and a low thermal resistance path to thePCB. The top-clip is then soldered to the silicon die toprovide SOURCE and GATE connections, eliminating thewires and reducing Package resistance and end result is a Package that on one side looks likea standard SO8IC and the other side looks like a miniatureDPAK. See Figure 2. Al Wire, Ribbon & Wire, Cu Clip & Au Bump, Cu Wire, Cu Clip & Wire and LFPAK [1]Below is a table listing some of the different names given to this Package by different 1. DIFFERENT VENDORS OFFERING THIS POWER Package WITH THEIR RESPECTIVE Package NAMESV ishayPowerPAK SO 8 International RectifierPQFNT exas InstrumentSON 5 6 mm (Q5A)Alpha and OmegaDFN 5 6ST MicroelectronicsPowerFLATt5 6 ToshibaSOP AdvanceInfineonSuper SO8 NXPLFPAK (SOT669)RenesasWPAK(3F) / LFPAKF airchildPower 56 APECPMPAK 5 6 MagnaChipPowerDFN56 ROHMHSOP8 UBIQPRPAK56 NIKO SEMPDFN 5 6 NEC8-pin HVSONAND9137 and Footprint CompatibilityThere are many power MOSFET s available in the surfacemounted power SO8 Footprint .

4 The following picture(Figure 3) shows the different Package styles and eachvendor has their recommended PCB Footprint and eachdiffers from each other. There is no generic JEDEC standardfor Power-SO8 devices and therefore each vendor has itsown pad design . None of the manufacturers of all of thesedevices can guarantee with certainty that they can beinterchangeable with the other devices, hence the need tocome up with a Footprint that will cover as many of thesevariations as 3. Several Power SO8 Package Styles Available on the MarketIn an attempt to achieve Footprint compatibility NXPdesigned the Universal Footprint [1]. This design was testedand evaluated in our packaging lab and it proved to be verygood. During different evaluations, voids ranging from 6%to 22% were observed on certain packages and even inLFPAK. In order to improve these results a modification tothe solder stencil was made in order to minimize optimized solder stencil design proposed here (seeFigure 4) reduced voids significantly and the resultsobtained provided voids ranging from 2% to 7%.

5 AND9137 4. Universal Footprint Showing Solder Mask and Optimized Solder Stencil DetailsAND9137 ResultsUsing the Universal Footprint , an array of 8 4 devicesper board was designed to accommodate several parts perboard. Two different solder stencil patterns were evaluatedand the recommended Universal Footprint with both solderpaste designs is shown in Figure Solder Stencil DesignOptimized Solder Stencil DesignFigure 5. Universal Footprint with Solder PasteAfter solder paste was applied parts placed using standard pick and place equipment. Boards were reflowed using Pb-Freesolder profile. Optimized Stencil array is shown in Figure 6 6. Universal Footprint Optimized Stencil Board ArrayAND9137 results of the optimized stencil are shown in Figure 7. X-Ray Images Showing LFPAK and SO8FL packages afterSolder Reflow using Optimized Solder Stencil PatternAND9137 were cross sectioned to verify solder thickness uniformity and quality. Those results can be seen in Figures 8 and 8.

6 Cross Sections of Board Mount. Solder Thickness Variation across PackageFigure 9. Detail on Solder Thickness Variation Across PackageConclusionThe need for a Footprint that can accommodate as manypower SO8 versions as possible has been addressed by thecreation of NXP s Universal Footprint . After evaluation ofthis Footprint improvements to solder attach voiding weremade by optimizing the solder stencil. Therecommendations provided here need to be evaluated andcharacterized by the end user in their equipment. The exactprofile will be determined by the Process Engineer based onthe board density and thickness. These variations willrequire small changes in the profile in order to achieve anoptimized TypeAny standard lead free solder paste commonly used on theindustry should work with this Package . The IPC SolderProducts Value Council has recommended Cu SAC alloy to be the lead free solderpaste alloy of choice for the electronics industry.

7 Solderpaste such as Cookson Electronics P/N WS3060 witha Type 3 or smaller sphere size is recommended. TheWS3060 has a water soluble flux for cleaning. CooksonElectronics P/N C0106A can be used if a no-clean flux Screening onto the PCBS tencil screening the solder onto the PCB is commonlyused in the industry. It is estimated that 60% of all assemblyerrors are due to paste printing. For a controlled, highyielding manufacturing process, it is one of the importantsteps of assembly. The recommended stencil thickness usedis mm ( in) and the sidewalls of the stencilopenings should be tapered approximately 5 along with anelectro-polish finish to aid in the release of the paste whenthe stencil is removed from the a typical edge PCB terminal pad, the stencil openingshould be the same size as the PCB mounting pad. However,in cases where the main device pad is soldered to the PCB,the stencil opening must be divided into a grid allowingchannels for gases to vent as shown in Figure 10.

8 Dividingthe larger pad into smaller screen openings reduces the riskof solder voiding and allows the solder joints for smallerterminal pads to be at the same height as the larger 10. Solder Stencil Design Illustrating how Stencil Openingsare Divided into an Array for Large Device AreasAND9137 Placement onto the PCBPick and place equipment with the standard tolerance of mm or better is recommended. The Package will tendto center itself and correct for slight placement errors duringreflow process due to surface tension of the ReflowOnce the Package is placed on the PCB along with thesolder paste, a standard surface mount reflow process can beused to solder the part. Figures 11 is an example of standardreflow profiles for typical Lead-Free solder optimum reflow profile used for every product andoven is different. Even the same equipment in a differentfacility may require an adjustment in the profile. The properramp and soak rates are determined by the solder pastevendor for their specific products.

9 Obtaining thisinformation from the paste vendor is highly recommendedsince the chemistry and viscosity of the flux matrix will exact profile will be determined by the ProcessEngineer based on the board density and thickness. Thesevariations will require small changes in the profile in orderto achieve an optimized 11. Typical Reflow Profile for Standard Pb-Free SolderIn general, the temperature of the part should not be raisemore than 2 C/sec during the initial stages of the reflowprofile. The soak zone then occurs when the part isapproximately 150 C and should last for 60 to 180 secondsfor Pb-free profiles. Typically, extending the time in the soakzone will reduce the risk of voiding within the solder. Thetemperature is then raised and will be above the liquid stateof the solder for 60 to 150 seconds for Pb-free depending onthe mass of the board. The peak temperature of the profileshould be between 245 and 260 C for Pb-free solder required, removal of the residual solder flux can becompleted by using the recommended procedures set forthby the flux Solder InspectionThe inspection of the solder joints is commonlyperformed with the use of X-Ray inspection system.

10 Withthis tool, one can locate defects such as shorts between pads,open contacts, voids within the solder as well as anyextraneous addition to searching for defects, the mounted deviceshould be rotated on its side to inspect the sides of the solderjoints with an X-Ray inspection system. The solder jointsshould have enough solder volume with the proper stand-offheight so that an hour glass shaped connection is notformed as shown in Figure 12. Hour glass solder joints area reliability concern and must be 12. Side View of DFN 8 Attachment Illustrating Preferred and Undesirable Solder Joint ShapesAND9137 [1] LFPAK The toughest Power SO8. NXP BVpublication 2009 [2]AND8195/D Board Mounting Notes for SO8 FlatLead. ON Semiconductor April 2007[3] NXP Universal Footprint Evaluations done by PhilCelaya and Stephen StGermann. ON Semiconductor8/2010 and 9/2010 PUBLICATION ORDERING INFORMATIONN. American Technical Support: 800 282 9855 Toll FreeUSA/CanadaEurope, Middle East and Africa Technical Support:Phone: 421 33 790 2910 Japan Customer Focus CenterPhone: 81 3 5817 1050 AND9137/DLITERATURE FULFILLMENT:Literature Distribution Center for ON Box 5163, Denver, Colorado 80217 USAP hone: 303 675 2175 or 800 344 3860 Toll Free USA/CanadaFax: 303 675 2176 or 800 344 3867 Toll Free USA/CanadaEmail: Semiconductor Website: Literature: additional information, please contact your localSales RepresentativeON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property.