Dual D-type flip-flop

1 HEF4013 BDual D-type flip -flopRev. 10 23 November 2021 Product data sheet1. General descriptionThe HEF4013B is a dual D-type flip -flop with set and reset; positive-edge trigger. Inputs includeclamp diodes. This enables the use of current limiting resistors to interface inputs to voltages inexcess of Features and benefits Wide supply voltage range from V to V CMOS low power dissipation High noise immunity Tolerant of slow clock rise and fall times Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from -40 C to +125 C Complies with JEDEC standard JESD 13-B ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-B exceeds 200 V3.

2 Applications Counters and dividers Registers Toggle flip -flops4. Ordering informationTable 1. Ordering informationPackageType numberTemperature rangeNameDescriptionVersionHEF4013BT-40 C to +125 CSO14plastic small outline package; 14 leads;body width mmSOT108-1 HEF4013 BTT-40 C to +125 CTSSOP14plastic thin shrink small outline package;14 leads; body width mmSOT402-1 NexperiaHEF4013 BDual D-type flip -flop5. Functional diagram001aag0841SD1D1CP1CD2SD2D2Q2Q1Q1Q 1312122CP2CD6534891110 SDCDDQFF1 CPQSDCDDQFF2 CPQFig. diagramDSDCDCPCC001aag086 CCCCCCCCQQFig. diagram (one flip -flop)HEF4013 BAll information provided in this document is subject to legal disclaimers.

3 Nexperia 2021. All rights reservedProduct data sheetRev. 10 23 November 20212 / 14 NexperiaHEF4013 BDual D-type flip -flop6. Pinning PinningHEF4013B1 QVDD1Q2Q1CP2Q1CD2CP1D2CD1SD2 DVSS2SD001aag0851234567810912111413 Fig. configuration for SOT108-1 (SO14) and SOT402-1 (TSSOP14) Pin descriptionTable 2. Pin descriptionSymbolPinDescription1Q, 2Q1, 13true output1Q, 2Q2, 12complement output1CP, 2CP3, 11clock input (LOW to HIGH edge-triggered)1CD, 2CD4, 10asynchronous clear-direct input (active HIGH)1D, 2D5, 9data input1SD, 2SD6, 8asynchronous set-direct input (active HIGH)VSS7ground (0 V)VDD14supply voltage7.

4 Functional descriptionTable 3. Function tableH = HIGH voltage level; L = LOW voltage level; X = don t care; = LOW-to-HIGH clock LLHLL HHLHEF4013 BAll information provided in this document is subject to legal disclaimers. Nexperia 2021. All rights reservedProduct data sheetRev. 10 23 November 20213 / 14 NexperiaHEF4013 BDual D-type flip -flop8. Limiting valuesTable 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).SymbolParameterConditionsMinMax UnitVDDsupply +18 VIIK input clamping currentVI < V or VI > VDD + V- 10mAVIinput + clamping currentVO < V or VO > VDD + V- 10mAII/Oinput/output current- 10mAIDD supply current-50mATstgstorage temperature-65+150 CTambambient temperature-40+125 CPtottotal power dissipationTamb = -40 C to +125 C[1]-500mWPpower dissipationper output-100mW[1]For SOT108-1 (SO14) package: Ptot derates linearly with mW/K above 100 SOT402-1 (TSSOP14) package: Ptot derates linearly with mW/K above 81 Recommended operating conditionsTable 5.

5 Recommended operating conditionsSymbolParameterConditionsMinMa xUnitVDDsupply voltage315 VVIinput voltage0 VDDVT ambambient temperature-40+125 CVDD = 5 s/VVDD = 10 s/V t/ Vinput transition rise and fall rateVDD = 15 s/VHEF4013 BAll information provided in this document is subject to legal disclaimers. Nexperia 2021. All rights reservedProduct data sheetRev. 10 23 November 20214 / 14 NexperiaHEF4013 BDual D-type flip -flop10. Static characteristicsTable 6. Static characteristicsVSS = 0 V; VI = VSS or VDD; unless otherwise = -40 CTamb = +25 CTamb = +85 CTamb = +125 CSymbolParameterConditionsVDDMinMaxMinMa xMinMaxMinMaxUnit5 voltage|IO| < 1 A15 voltage|IO| < 1 A15 voltage|IO| < 1 A15 voltage|IO| < 1 A15 = V5 = V5 = V10 currentVO = V15 = V5 = V10 currentVO = V15 leakagecurrent15 V- A5 A10 AIDD supply currentall valid inputcombinations;|IO| = 0 A15 information provided in this document is subject to legal disclaimers.

6 Nexperia 2021. All rights reservedProduct data sheetRev. 10 23 November 20215 / 14 NexperiaHEF4013 BDual D-type flip -flop11. Dynamic characteristicsTable 7. Dynamic characteristicsTamb = 25 C, unless otherwise specified. For test circuit see Fig. formulaMinTypMaxUnit5 V[1]83 + CL-110220ns10 V34 + CL-4590nsnCP to nQ, nQ;see Fig. 415 V22 + CL-3060ns5 V[1]73 + CL-100200ns10 V29 + CL-4080nsnSD to nQ15 V22 + CL-3060ns5 V[1]73 + CL-100200ns10 V29 + CL-4080nstPHLHIGH to LOWpropagation delaynCD to nQ15 V22 + CL-3060ns5 V[1]68 + CL-95190ns10 V29 + CL-4080nsnCP to nQ, nQ;see Fig.

7 415 V22 + CL-3060ns5 V[1]48 + CL-75150ns10 V24 + CL-3570nsnSD to nQ15 V17 + CL-2550ns5 V[1]33 + CL-60120ns10 V19 + CL-3060nstPLHLOW to HIGH propagation delaynCD to nQ15 V12 + CL-2040ns5 V[1]10 + CL-60120ns10 V9 + CL-3060nstttransition timesee Fig. 415 V6 + CL-2040ns5 V4020-ns10 V2510-nstsuset-up timenD to nCP; see Fig. 415 V155-ns5 V200-ns10 V200-nsthhold timenD to nCP; see Fig. 415 V150-ns5 V6030-ns10 V3015-nsnCP input LOW;see Fig. 415 V2010-ns5 V5025-ns10 V2412-nsnSD input HIGH;see Fig. 515 V2010-ns5 V5025-ns10 V2412-nstWpulse widthnCD input HIGH;see Fig. 515 V2010-nsHEF4013 BAll information provided in this document is subject to legal disclaimers.

8 Nexperia 2021. All rights reservedProduct data sheetRev. 10 23 November 20216 / 14 NexperiaHEF4013 BDual D-type flip -flopSymbolParameterConditionsVDDE xtrapolation formulaMinTypMaxUnit5 V+15-5-ns10 V150-nsnSD input; see Fig. 515 V150-ns5 V4025-ns10 V2510-nstrecrecovery timenCD input; see Fig. 515 V2510-ns5 V714-MHz10 V1428-MHzfclk(max)maximum clockfrequencysee Fig. 415 V2040-MHz[1]Typical values of the propagation delays and output transition times can be calculated with the extrapolation formulas (CL in pF).Table 8. Dynamic power dissipationVSS = 0 V; tr = tf 20 ns; Tamb = 25 formulaWhere5 VPD = 850 fi + (fo CL) VDD 2 W10 VPD = 3600 fi + (fo CL) VDD 2 WPDdynamic power dissipation15 VPD = 9000 fi + (fo CL) VDD 2 Wfi = input frequency in MHz;fo = output frequency in MHz;CL = output load capacitance in pF; (fo CL) = sum of the outputs.

9 VDD = supply voltage in Waveforms and test circuit001aah0160 V0 Vthtsu1/fclk(max) thtsutftrtWVMVMVM VIVOHVOLVI output nQinput nCPinput nDtttttPHLtPLH VYVXSet-up and hold times are shown as positive values but may be specified as negative shaded areas indicate when the input is permitted to change for predictable output levels: VOL and VOH are typical output voltage levels that occur with the output points are given in Table time, hold time, minimum clock pulse width, propagation delays and transition timesHEF4013 BAll information provided in this document is subject to legal disclaimers. Nexperia 2021.

10 All rights reservedProduct data sheetRev. 10 23 November 20217 / 14 NexperiaHEF4013 BDual D-type flip -flop001aag088input nSDinput nCDinput nCPVI0 V0 VVOL0 VVIVIVOHtWVMtWVMVM output nQtrectrecRecovery times are shown as positive values but may be specified as negative levels: VOL and VOH are typical output voltage levels that occur with the output points are given in Table , nCD recovery time and pulse widthTable 9. Measurement pointsSupply voltageInputOutputVDDVMVMVXVY5 V to 15 and measurement data is given in Table 10;Definitions test circuit:RT = Termination resistance should be equal to output impedance Zo of the pulse = Load capacitance including jig and probe circuit for measuring switching timesTable 10.